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never stop thinking. hyb18t1g400af hyb18t1g800af hyb18t1g160af 1-gbit double-data-rate-two sdram ddr2 sdram rohs compliant products data sheet, rev. 1.02, nov. 2004 memory products
the information in this document is subject to change without notice. edition 2004-11 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb18t1g400af hyb18t1g800af hyb18t1g160af 1-gbit double-data-rate-two sdram ddr2 sdram rohs compliant products data sheet, rev. 1.02, nov. 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hyb18t1g[40/80/16]0af?[3.7/5] revision history: 2004-11 rev. 1.02 previous version: 2004-03-24 (v1.0) page subjects (major changes since last revision) all document contains final currents all document contains green products only we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram data sheet 5 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 1gbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6 input/output functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.7 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1 simplified state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 basic functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.2 programming the mode register and extended mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.2.1 ddr2 sdram mode register set (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 2.2.3 ddr2 sdram extended mode register set (emrs(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.3.1 emr(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.3.2 emr(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3 off-chip driver (ocd) impedance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4 on-die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5 bank activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.6 read and write commands and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.1 posted cas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.2 burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.3 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.4 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.5 write data mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.6 burst interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.7 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.1 read operation followed by a precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.2 write followed by precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.8 auto-precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.8.1 read with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.8.2 write with auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.8.3 read or write to precharge command spacing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8.4 concurrent auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.9 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.9.1 auto-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.9.2 self-refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.10 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.11 other commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.11.1 no operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.11.2 deselect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.12 input clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.13 asynchronous cke low reset event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.2 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.4 default output v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table of contents
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram data sheet 6 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.4.1 calibrated output driver v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.6 power & ground clamp v-i characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2 on die termination (odt) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8 ac timing measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1 reference load for timing measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2 slew rate measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2.1 output slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.2.2 input slew rate - differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.3 input and data setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.1 definition for input setup ( t is ) and hold time ( t ih ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes . . . . . . . . . . . . . . . . 87 8.3.3 definition for data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes . . . . . . . . . . . . . 88 8.3.4 slew rate definition for input and data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10 ddr2 component nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table of contents
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 7 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1overview this chapter gives an overview of the 1-gbit double -data-rate-two sdram product family and describes its main characteristics. 1.1 features the 1-gbit double-data-rate-two sdram offers the following key features: ? 1.8 v 0.1 v power supply 1.8 v 0.1 v (sstl_18) compatible i/o dram organisations with 4, 8 and 16 data in/outputs double data rate architecture: two data transfers per clock cycle, eight internal banks for concurrent operation cas latency: 3, 4 and 5 burst length: 4 and 8 differential clock inputs (ck and ck ) bi-directional, differential data strobes (dqs and dqs ) are transmitted / received with data. edge aligned with read data and center-aligned with write data. dll aligns dq and dqs transitions with clock dqs can be disabled for single-ended data strobe operation commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs data masks (dm) for write data posted cas by programmable additive latency for better command and data bus efficiency off-chip-driver impedance adjustment (ocd) and on-die-termination (odt) for better signal quality. auto-precharge operation for read and write bursts auto-refresh, self-refresh and power saving power-down modes average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c strong and weak strength data-output drivers 1k page size for 4 & 8, 2k page size for 16 packages: p-tfbga-68 for 4 & 8 components p-tfbga-92 for 16 components rohs compliant products 1) 1) rohs compliant product: restriction of the use of certai n hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include merc ury, lead, cadmium, hexavalent chro mium, polybrominated biphenyls and polybrominated biphenyl ethers. table 1 high performance product type speed code ?3.7 ?5 unit speed grade ddr2?533 4?4?4 ddr2?400 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 40 ns min. row cycle time t rc 60 55 ns
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 8 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1.2 description the 1-gb ddr2 dram is a high-speed double-data- rate-2 cmos synchronous dram device containing 1,073,741,824 bits and internally configured as an octal-bank dram. the 1-gb device is organized as either 32 mbit 4 i/o 8 banks, 16 mbit 8 i/o 8 banks or 8 mbit 16 i/o 8 banks chip. these synchronous devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. see table 1 for performance figures. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. off-chip driver (ocd ) impedance adjustment 5. on-die terminatio n (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of differential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 17 bit address bus for 4 and 8 organised components and a 16 bit address bus for 16 components is used to convey row, column and bank address information in a ra s-cas multiplexing style. the ddr2 device operates with a 1.8 v 0.1 v power supply. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in p-tfbga package. 1.3 ordering information note: for product nomenclature see chapter 10 of this data sheet table 2 ordering information for rohs compliant products part number org. speed cas 1) -rcd 2) -rp 3) latencies 1) cas: column adress strobe 2) rcd: row column delay 3) rp: row precharge clock (mhz) cas 1) -rcd 2) -rp 3) latencies clock (mhz) package hyb18t1g400af?5 x4 ddr2?400 3?3?3 200 ? ? p-tfbga-68 hyb18t1g800af?5 x8 hyb18t1g160af?5 x16 p-tfbga-92 hyb18t1g400af?3.7 x4 ddr2?533 4?4?4 266 3?3?3 200 p-tfbga-68 hyb18t1g800af?3.7 x8 hyb18t1g160af?3.7 x16 p-tfbga-92
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 9 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1.4 pin configuration the pin configuration of a ddr2 s dram is listed by function in table 3 . the abbreviations used in the pin#/buffer type columns are explained in table 4 and table 5 respectively. the pin numbering for the fbga package is depicted in figure 1 for 4, figure 2 for 8 and figure 3 for 16 . table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals 4/ 8 organizations j8 ck i sstl clock signal k8 ck i sstl complementary clock signal k2 cke i sstl clock enable clock signals 16 organization m8 ck i sstl clock signal n8 ck i sstl complementary clock signal n2 cke i sstl clock enable control signals 4/ 8 organizations k7 ras i sstl row address strobe l7 cas i sstl column address strobe k3 we i sstl write enable l8 cs i sstl chip select control signals 16 organization n7 ras i sstl row address strobe p7 cas i sstl column address strobe n3 we i sstl write enable p8 cs i sstl chip select address signals 4/ 8 organizations l2 ba0 i sstl bank address bus 2:0 l3 ba1 i sstl l1 ba2 i sstl m8 a0 i sstl address signal 12:0 m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 10 rev. 1.02, 2004-11 09112003-7yzf-nh5g r8 a13 i sstl address signal 13 address signals 16 organization p2 ba0 i sstl bank address bus 2:0 p3 ba1 i sstl p1 ba2 i sstl r8 a0 i sstl address signal 12:0 r3 a1 i sstl r7 a2 i sstl t2 a3 i sstl t8 a4 i sstl t3 a5 i sstl t7 a6 i sstl u2 a7 i sstl u8 a8 i sstl u3 a9 i sstl r2 a10 i sstl ap i sstl u7 a11 i sstl v2 a12 i sstl data signals 4/ 8 organizations g8 dq0 i/o sstl data signal 0 g2 dq1 i/o sstl data signal 1 h7 dq2 i/o sstl data signal 2 h3 dq3 i/o sstl data signal 3 data signals 8 organization h1 dq4 i/o sstl data signal 4 h9 dq5 i/o sstl data signal 5 f1 dq6 i/o sstl data signal 6 f9 dq7 i/o sstl data signal 7 data signals 16 organization k8 dq0 i/o sstl data signal 0 k2 dq1 i/o sstl data signal 1 l7 dq2 i/o sstl data signal 2 l3 dq3 i/o sstl data signal 3 l1 dq4 i/o sstl data signal 4 l9 dq5 i/o sstl data signal 5 j1 dq6 i/o sstl data signal 6 j9 dq7 i/o sstl data signal 7 f8 dq8 i/o sstl data signal 8 f2 dq9 i/o sstl data signal 9 table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 11 rev. 1.02, 2004-11 09112003-7yzf-nh5g g7 dq10 i/o sstl data signal 10 g3 dq11 i/o sstl data signal 11 g1 dq12 i/o sstl data signal 12 g9 dq13 i/o sstl data signal 13 e1 dq14 i/o sstl data signal 14 e9 dq15 i/o sstl data signal 15 data strobe 4 / 8 organisations f7 dqs i/o sstl data strobe e8 dqs i/o sstl data strobe data strobe 8 organisations f3 rdqs i/o sstl read data strobe e2 rdqs i/o sstl read data strobe data strobe 16 organization e7 udqs i/o sstl data strobe upper byte d8 udqs i/o sstl data strobe upper byte j7 ldqs i/o sstl data strobe lower byte h8 ldqs i/o sstl data strobe lower byte data mask 4 / 8 organizations e3 dm i sstl data mask data mask 16 organization f3 udm i sstl data mask upper byte j3 ldm i sstl data mask lower byte power supplies 4/ 8 organizations e9,g1,g3,g7, g9 v ddq pwr ? i/o driver power supply e1,j9,m9,r1 v dd pwr ? power supply e7,f2,f8,h2, h8 v ssq pwr ? power supply e3,j3;n1,p9 v ss pwr ? power supply j2 v ref ai ? i/o reference voltage j1 v ddl pwr ? power supply j7 v ssdl pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply m1 v ddl pwr ? power supply d1,h1,m9,r9, v1 v dd pwr ? power supply table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 12 rev. 1.02, 2004-11 09112003-7yzf-nh5g d7,e2,g2,e8, g8,h7,j2,j8,l 2,l8 v ssq pwr ? power supply m7 v ssdl pwr ? power supply d3,h3,m3,t1, u9 v ss pwr ? power supply not connected 4 organization a1,a2,a8,a9, e2,f9,h1,f1, r7,h9,w1,w2 ,w8,w9,r3 nc nc ? not connected not connected 8 organization a1,a2,a8,a9, r7,w2,w3,w 8,w9,r3 nc nc ? not connected not connected 16 organization a1,a2,a8,a9, d2,h2,v3,v7, v8,aa1,aa2,a a8,aa9 nc nc ? not connected other pins 4/ 8 organizations k9 odt i sstl on-die termination control other pins 16 organization n9 odt i sstl on-die termination control table 4 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 5 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 13 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 1 pin configuration p-tfbga-68 ( 4) top view, see the balls throught the package note: v ddl and v ssdl are power and ground for the dll.they are connected on the device to v dd and v ss - 0 0 4 ! " # $ & ' ( * % , + # 3 ! ! ! $ 1 $ 1 3 6 3 3 $ , 6 3 3 1 6 $ $ 1 6 3 3 1 ! . # ! 6 $ $ 1 . # $ 1 . # # + # ! 3 $ 1 3 6 $ $ 1 6 3 3 1 # + 6 $ $ 2 ! 3 / $ 4 6 $ $ ! 6 3 3 ! " ! . # . # 6 2 % & . # ! ! 0 ! ! ! ! ! ! . # $ 1 $ - 6 3 3 6 $ $ 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 6 $ $ , 6 3 3 # + % 7 % " ! " ! 6 3 3 6 $ $ - . 0 2 4 5 6 7 . # . # . # . # . # . # . # . #
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 14 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 2 pin configuration p-tfbga-68 ( 8) top view, see the balls throught the package note 1. rdqs / rdqs are enabled by emrs(1) command. 2. if rdqs / rdqs is enabled, the dm function is disabled 3. when enabled, rdqs & rdqs are used as strobe signals during reads. 4. v ddl and v ssdl are power and ground for the dll.they are connected on the device to v dd and v ss - 0 0 4 # 3 " ! $ 1 $ 1 6 2 % & . 5 2 $ 1 3 ! ! 0 ! ! ! ! ! ! . # $ 1 $ - 2 $ 1 3 6 3 3 ! ! ! $ 1 $ 1 3 6 3 3 $ , 6 3 3 1 6 $ $ 1 6 3 3 1 ! . # ! 6 $ $ 1 $ 1 $ 1 $ 1 ! " # $ & ' ( * % , + 6 $ $ 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 6 3 3 1 6 $ $ , 6 3 3 # + % 7 % # + " ! " ! 6 3 3 6 $ $ # ! 3 $ 1 3 6 $ $ 1 6 3 3 1 # + 6 $ $ 2 ! 3 / $ 4 6 $ $ ! 6 3 3 ! - . 0 2 4 5 6 7 . # . # . # . # . # . # . # . #
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 15 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 3 pin configuration p-tfbga-92 ( 16) top view, see the balls throught the package note 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ssdl are power and ground for the dll.they are connected on the device to v dd and v ss - 0 0 4 # 3 " ! $ 1 ! ! 0 ! ! ! ! ! ! . # 6 3 3 ! ! ! $ 1 5 $ 1 3 6 3 3 $ , 6 3 3 1 6 $ $ 1 6 3 3 1 ! . # ! 6 $ $ 1 $ 1 $ 1 $ 1 ! " # $ & ' ( * % , + 6 $ $ 6 3 3 1 6 $ $ 1 $ 1 6 $ $ 1 7 % # + " ! " ! 6 3 3 6 $ $ # ! 3 5 $ 1 3 6 $ $ 1 6 3 3 1 # + 6 $ $ 2 ! 3 / $ 4 6 $ $ ! 6 3 3 . # - . 2 0 . # 5 $ - . # 6 3 3 $ 1 6 3 3 1 , $ - 6 $ $ 1 $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 $ 1 6 3 3 1 $ 1 6 $ $ , 6 2 %& 6 3 3 # + % 6 3 3 1 , $ 1 3 6 $ $ 1 , $ 1 3 6 3 3 1 $ 1 6 $ $ 1 $ 1 6 $ $ 1 $ 1 6 3 3 1 $ 1 6 $ $ 4 5 6 7 8 ! ! . # . # . # . # . # . # . # . #
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 16 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1.5 1gbit ddr2 addressing 1.6 input/output functional description table 6 1 gbit ddr2 addressing configuration 256 mb x 4 128 mb x 8 64 mb x 16 note number of banks 8 8 8 bank address ba[2:0] ba[2:0] ba[2:0] auto-precharge a10 / ap a10 / ap a10 / ap row address a[13:0] a[13:0] a[12:0] column address a11, a[9:0] a[9:0] a[9:0] number of column address bits 11 10 10 1) 1) refered to as ?colbits? number of i/os 4 8 16 2) 2) refered to as ?org? page size [bytes] 1024 (1k) 1024 (1k) 2048 (2k) 3) 3) table 7 input/output functional description symbol type function ck, ck input clock: ck and ck are differential system clock inputs. all address and control inputs are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossing of ck and ck (both direction of crossing) cke input clock enable: cke high activates and cke low d eactivates internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refresh operation (all ba nks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit and for self- refresh entry.input buffers excluding cke are disabled during self-refresh. cke is used asynchronously to detect self-refresh exit co ndition. self-r efresh termination itself is synchronous. after v ref has become stable during power-on and initialisation sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. cs input chip select: all command are masked when cs is registered high. cs provides for external rank selection on systems with multiple memory ranks. cs is considered part of the command code. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm, ldm, udm input input data mask: dm is an input mask si gnal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ldm and udm are the input mask signals for x16 components and control the lower or upper bytes. for x8 components the data mask function is disabled, when rdqs / rqds are enabled by emrs(1) command. pagesize 2 colbits org 8 -------- = bytes []
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 17 rev. 1.02, 2004-11 09112003-7yzf-nh5g ba0, ba1, ba2 input bank address inputs: ba0, ba1, ba2 define to which of the 8 internal memory banks an activate, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a[9:0], a10/ap, a[13:11] input address inputs: provides the row address for activate commands and the column address and auto-precharge bit a10 (=ap) for read/write commands to select one location out of the memory array in the respective bank. a10(=ap) is sampled during a precharge command to determine whether the precharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is to be precharged, the bank is selected by ba0, ba1 and ba2. the address inputs also provide the op-code during mode register set commands. row address a13 is used on x4 and x8 components only. dqx input / output data inputs/output: bi-directional data bus. dq[3:0] for x4 components, dq[7:0] for x8 components and dq[15:0] for x16 components dqs, (dqs ) ldqs, (ldqs ) udqs, (udqs ) input / output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the x16, ldqs corresponds to the data on dq[7:0]; udqs corresponds to the data on dq[15:8]. the datastrobes dqs, ldqs, udqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs , udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals. rdqs, (rdqs ) input / output read data strobe: for the x8 components a rdqs, rdqs pair can be enabled via the emrs(1) for read timing.rdqs, rdqs is not supported on x4 and x16 components. rdqs, rdqs are edge-aligned with read data. if rdqs, rdqs is enabled, the dm function is disabled on x8 components. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is applied to each dq, dqs, dqs and dm signal for x4 an d dq, dqs, dqs , rdqs, rdqs and dm for x8 configurations. for x16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the ex tended mode register (emrs(1)) is programmed to disable odt. nc ? no connect: no internal electrical connection is present v ddq supply dq power supply: 1.8 v v ssq supply dq ground v ddl supply dll power supply: 1.8 v v ssdl supply dll ground v dd supply power supply: 1.8 v v ss supply ground v ref supply reference voltage: 0.9 v ( v ddq /2) table 7 input/output functional description symbol type function
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 18 rev. 1.02, 2004-11 09112003-7yzf-nh5g 1.7 block diagrams figure 4 block diagram 32mbit x 4 i/o x 8 banks notes 1. 256mb x 4 organisation with 14 row, 3 bank and 11 column external addresses 2. this functional block diagram is intended to facilitate user understanding of the oper ation of the device; it does not represent an actual circuit implementation. 3. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. mpbt0240 column decoder column decoder column decoder column decoder column decoder column decoder column decoder column decoder control logic row-address mux 16384 i/o gating dm mask logic 8192 refresh counter 14 3 3 column-address counter/latch 9 2 col0,1 address register 11 14 17 mode regis ters command decode ras cas we cs ck ck cke a0 - a13, ba0, ba2 16 4 4 1 4 4 16 data mask write fifo & drivers 16 col0,1 ck, ck receivers input register mux col0,1 dqs generator drivers 4 2 data dq s, dq s read latch 16 dll ck, ck 17 14 4 4 4 4 1 1 1 1 4 4 1 1 1 1 8 8 dqs,d qs dq0- dq3 odt control dm odt 4 4 4 4 bank 0 bank 1 row-address latch & decoder bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 512(x16) bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 memory array (1 6 3 84 x 5 1 2 x 16 ) sense amplifier bank 0 bank control logic
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 19 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 5 block diagram 16mbit x 8 i/o x 8 banks notes 1. 128mb x 8 organisation with 14 row, 3 bank and 10 column external addresses 2. this functional block diagram is intended to facilitate user understanding of the oper ation of the device; it does not represent an actual circuit implementation. 3. dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional dq and dqs signals. mpbt0230 column decoder column decoder column decoder column decoder column decoder column decoder column decoder column decoder control logic row-address mux 16 3 8 4 i/o gating dm mask logic 8192 refresh counter 14 3 3 column-address counter/latch 8 2 col0,1 address register 10 14 17 mode registers command decode ras cas we cs ck ck cke a0 - a13, ba0, ba2 32 8 8 1 8 4 32 data mask write fifo & drivers 32 col0,1 ck, ck receivers input register mux col0,1 dqs generator drivers 8 2 data dq s, dq s read latch 32 dll ck, ck 17 14 8 8 8 8 1 1 1 1 8 8 1 1 1 1 8 8 dqs,d qs dq0- dq7 odt control dm rd qs, rd qs odt 8 8 8 8 bank 0 bank 1 row-address latch & decoder bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 256 (x32) bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 memory array (16384 x 256 x 32) sense amplifier bank 0 bank control logic
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram overview data sheet 20 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 6 block diagram 8mbit x 16 i/o x 8 banks notes 4. 64mb 16 organisation with 13 row, 3 bank and 10 column external adresses 5. this functional block diagram is intended to facilitate user understanding of the oper ation of the device; it does not represent an actual circuit implementation. 6. ldm, udm is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional ldqs and udqs signals. mpbt0220 column decoder column decoder column decoder column decoder column decoder column decoder column decoder column decoder control logic row-address mux 8192 i/o gating dm mask logic 16384 refresh counter 13 3 3 column-address counter/latch 8 2 col0,1 address register 10 13 16 mode registers command decode ras cas we cs ck ck cke a0 - a12, ba0, ba2 64 16 16 2 16 8 64 data mask write fifo & driv ers 64 col0,1 ck, ck receivers input register mux col0,1 dq s generator drivers 16 4 data dq s, dq s read latch 64 dll ck, ck 16 13 16 16 16 16 2 2 2 2 16 16 2 2 2 2 8 8 udqs,udqs dq0- dq15 odt control udm, ldm ldqs, ldqs odt 16 16 16 16 bank 0 bank 1 row-address latch & decoder bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 256 (x64) bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 memory array (8192 x 256 x 64) sense amplifier bank 0 bank control logic
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 21 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2 functional description 2.1 simplified state diagram figure 7 simplified state diagram note: this simplified state diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. in particular situations involving more than one bank, enabling / disabling on-die termination, power-down entry / exit - among other things - are not captured in full detail. m pft0010 bank active reading_ap reading w ritin g _ a p w rite_ap w ritin g activating id le r l + b l /2 + t rtp s e ttin g mrs or emrs self refresh r e f s precharge pd in itia liz a tio n sequence a u to m a tic s e q u e n c e com m and sequence active pd ckel pd_entry ckeh write w r i t e r ead r e a d r ead_ap precharging pre r e a d _ a p w r i te _ a p t rp pre t rcd w l + b l /2 + w r a c t t mrd mrs pd_entry ckeh ckel ckel auto refreshing t rfc refa r e f s x
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 22 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.2 basic functionality read and write accesses to the ddr2 sdram are burst oriented; accesses star t at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto-precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following se ctions provide detailed information covering device initialization, register definition, command description and device operation. 2.2.1 power on and initialization ddr2 sdram?s must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power-up and initialization sequence the following sequence is required for power up and initialization. 1. apply power and attempt to maintain cke below 0.2 v ddq and odt at a low state (all other inputs may be undefined). to guarantee odt off, v ref must be valid and a low leve l must be applied to the odt pin. maximum power up interval for v dd / v ddq is specified as 10.0 ms. the power interval is defined as the amount of time it takes for v dd / v ddq to power-up from 0 v to 1.8 v 100 mv. at least one of these two sets of conditions must be met: ? v dd , v ddl and v ddq are driven from a single power converter output, and ? v tt is limited to 0.95 v max, and ? v ref tracks v ddq /2 or ?apply v dd before or at the same time as v ddq . ?apply v ddq before or at the same time as v tt & v ref . 2. start clock (ck, ck ) and maintain stable power and clock condition for a minimum of 200 s. 3. apply nop or deselect commands and take cke high. 4. continue nop or deselect commands for 400 ns, then issue a precharge all command. 5. issue emrs(2) command. 6. issue emrs(3) command. 7. issue emrs(1) command to enable dll. 8. issue a mrs command for ?dll reset?. 9. issue precharge-all command. 10. issue 2 or more auto-refresh commands. 11. issue the final mrs command to turn the dll on and to set the necessary operating parameter. 12. at least 200 clocks after step 8, issue emrs(1) commands to either execute the ocd calibration or select the ocd default. issue the final emrs(1) command to exit ocd calibration mode and set the necessary operating parameters. 13. the ddr2 sdram is now ready for normal operation.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 23 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 8 initialization sequence after power up 2.2.2 programming the mode register and ex tended mode registers for application flexibility, bu rst length, burst type, cas latency, dll reset function, write recovery time (wr) are user defined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, additive cas latency, driver impedance, on die termination (odt), single-ended strobe and off chip driver impedance adjustment (ocd) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) or extended mode registers (emr(1, 2, 3)) can be altered by re-executing the mrs and emrs commands. if the user chooses to modify only a subset of the mr or emr variables, all variables must be redefined when the mrs or emrs commands are issued. after initial power up, a ll mrs and emrs commands must be issued before read or write cycles may begin. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. either mrs or emrs commands are activated by the low signals of cs , ras , cas and we at the positive edge of the clock. when all bank addresses ba[2:0] are 0, the ddr2 sdram enables the mrs command. when the bank addresses ba0 is 1 and ba[2:1] are 0, the ddr2 sdram enables the emrs(1) command. the address input data during this cycle defines the parameters to be set as shown in the mrs and emrs tables. a new command may be issued after the mode register set command cycle time ( t mrd ). mrs, emrs and dll reset do not affect array contents, which means reinit ialization including those can be executed any time after power-up without affecting array contents. 2.2.2.1 ddr2 sdram m ode register set (mrs) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs cas latency, burst length, burst sequence, test mode, dll reset, write recovery (wr) and various vendor specific options to make ddr2 sdram useful for various applications. the default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba[2:0], while controlling the state of address pins a[13:0]. the ddr2 sdram should be in all bank precharged (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time ( t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. the mode register is divided into various fields depending on functionality. burst length is defined by a[2:0] with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a[6:4]. a7 is used for test mode and must be set to 0 for normal dram operation. a8 is used for dll reset. a[11:9] are used for write recovery time (wr) definition for auto-precharge mode. with address bit a12 two power-down modes can be selected, a ?standard mode? and a ?low-power? power-down mode, where the dll is disabled. address bit a13 and all ?higher? address bits (including ba2) have to be set to 0 for compatibility with other ddr2 memory products with higher memory densities. 1st auto refresh ck, ck mrs pre all emrs(3) trp tmrs tmrs cke 400 ns nop odt "low" emrs(2) tmrs emrs(1) tmrs pre all trp trfc 2nd auto refresh trfc extended mode register(1) set with dll enable mode register set with dll reset min. 200 cycles to lock the dll mrs tmrs follow ocd flowchart emrs(1) ocd emrs(1) ocd any command ocd drive(1) or ocd default ocd calibration mode exit mode register set w/o dll reset tmrs
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 24 rev. 1.02, 2004-11 09112003-7yzf-nh5g mr mode register definition (ba[2:0] = 000 b ) ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 1) 1) a13 is only available for x4 and x8 configuration pd wr dll tm cl bt bl reg. addr w w ww www field bits type 1) 1) w = write only register bits description bl [2:0] w burst length 010 4 011 8 bt 3w burst type 0 sequential 1 interleaved cl [6:4] w cas latency note: all other bit combinations are illegal. 010 2 2) 011 3 100 4 101 5 2) cas latency 2 is optional for jedec compliant devices. this option is implemented in this device but is neither tested nor guaranteed. tm 7w test mode 0 normal mode 1 vendor specific test mode dll 8w dll reset 0no 1yes wr [11:9] w write recovery 3) note: all other bit combinations are illegal. 001 2 010 3 011 4 100 5 101 6 3) number of clock cycles for write reco very during auto-precharge. wr in cl ock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr[cycles] t wr (ns) / t ck (ns) the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing. w rmin is determined by t ckmax and w rmax is determined by t ckmin . pd 12 w active power-down mode select 0fast exit 1 slow exit
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 25 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.2.3 ddr2 sdram extended m ode register set (emrs(1)) the extended mode register emr(1) stores the data for enabling or disabling the dll, output driver strength, additive latency, ocd program, odt, dqs and output buffers disable, rqds and rdqs enable. the default value of the extended mode register emr(1) is not defined, therefore the extended mode register must be written after power-up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we , ba[2:1] and high on ba0, while controlling the st ate of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the emr(1). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. emr(1) extended mode register definition (ba[2:0] = 001 b ) ba2ba1ba0a13a12a11a10a9a8a7a6a5a4a3a2a1a0 0010 1) 1) a13 is only available for 4 and 8 configuration. q off rdqs dqs ocd program rtt al rtt dic dll reg. addr w w w w w w w w field bits type 1) description dll 0w dll enable 0 enable 1 disable dic 1w off-chip driver impedance control 0 normal (driver size = 100%) 1 weak (driver size = 60%) r tt 2,6 w nominal termination resistance of odt note: all other bit comb inations are illegal. 00 (odt disabled) 01 75 ohm 10 150 ohm al [5:3] w additive latency note: all other bit comb inations are illegal. 000 0 001 1 010 2 011 3 100 4 ocd program [9:7] w off-chip driver calibration program 000 ocd calibration mode exit, maintain setting 001 drive (1) 010 drive (0) 100 adjust mode 111 ocd calibration default dqs 10 w complement data strobe (dqs output) 0 enable 1 disable rdqs 11 w read data strobe output (rdqs, rdqs ) 0 disable 1 enable
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 26 rev. 1.02, 2004-11 09112003-7yzf-nh5g a0 is used for dll enable or disable. a1 is used for enabling half-strength data-output driver. a2 and a6 enables on-die termination (odt) and sets the rtt value. a[5:3] are used for additive latency settings and a[9:7] enables the ocd impedance adjustment mode. a10 enables or disables the differential dqs and rdqs signals, a11 disables or enables rdqs. address bit a12 have to be set to 0 for normal operation. with a12 set to 1 the sdram outputs are disabled and in hi-z. 1 on ba0 and 0 for ba[2:1] have to be set to access the emrs(1). a13 and all ?higher? address bits (including ba2) have to be set to 0 for compatibility with other ddr2 memory products with higher memory densities. refer to emr(1) . single-ended and differential data strobe signals table 8 lists all possible combinations for dqs, dqs , rdqs, rqds which can be programmed by a[11:10] address bits in emrs(1). rdqs and rdqs are available in 8 components only. if rdqs is enabled in 8 components, the dm function is disabled. rdqs is active for reads and don?t care for writes. dll enable/disable the dll must be enabled for normal operation. dll enable is required during po wer up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self-refresh operation and is automatically re- enabled and reset upon exit of self-refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for syn chronization to occur may result in a violation of the t ac or t dqsck parameters. output disable (qoff) under normal operation, the dram outputs are enabled during read operation for driving data (qoff bit in the emr(1) is set to 0). when the qoff bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure idd currents during read operations, without including the output buffer current and external load currents. 2.2.3.1 emr(2) the extended mode registers emr(2) and emr(3) are reserved for future use and must be programmed when setting the mode register during initialization. the extended mode register emr(2) is written by asserting low on cs , ras , cas , we , ba2, ba0 and high on ba1, while controlling the states of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time ( t mrd ) must be satisfied to complete the write operation to the emr(2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. qoff 12 w output disable 0 output buffers enabled 1 output buffers disabled 1) w = write only register bits field bits type 1) description (cont?d) table 8 single-ended and differential data strobe signals emrs(1) strobe function matrix signaling a11 (rdqs enable) a10 (dqs enable) rdqs/dm rdqs dqs dqs 0 (disable) 0 (enable) dm hi-z dqs dqs differential dqs signals 0 (disable) 1 (disable) dm hi-z dqs hi-z single-ended dqs signals 1 (enable) 0 (enable) rdqs rdqs dqs dqs differential dqs signals 1 (enable) 1 (disable) rdqs hi-z dqs hi-z single-ended dqs signals
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 27 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.2.3.2 emr(3) the extended mode register emr(3) is reserved for future use and all bits except ba0 and ba1 must be programmed to 0 when setting the mode register during initialization. emr(2) programming extended mode register definition (ba[2:0] = 010 b ) ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 010 0 1)2) 1) a13 is only available for 4 and 8 configuration. 2) must be programmed to ?0? reg.addr emr(3) programming extended mode register definition (ba[2:0] = 011 b ) ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 011 0 1)2) 1) a13 is only available for 4 and 8 configuration. 2) must be programmed to ?0? reg. addr
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 28 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.3 off-chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart below is an example of the sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) should be carefully controlled depending on system environment. figure 9 ocd impedance adjustment flow chart note: mr should be set before entering ocd impedance adjustment and odt should be carefully controlled depending on system environment m pft0020 start em rs: o cd calibration m ode exit need calibration emrs: enter adjust mode b l = 4 c o d e in p u t to a ll d q s inc, d ec or n o p e m r s : o c d c a lib ra tio n m o d e e x it e m r s : o c d c a lib ra tio n m o d e e x it emrs: drive (1) dq & dqs high; dqs low all ok emrs: drive (0) dq & dqs low; dqs high test test em rs: o cd calibration m ode exit emrs: enter adjust mode bl = 4 code input to all dq s inc, d ec or n o p need calibration em rs: o cd calibration m ode exit em rs: o cd calibration m ode exit end all ok
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 29 rev. 1.02, 2004-11 09112003-7yzf-nh5g extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the following emrs(1) mode. in dr ive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emr(1) bit enabling rdqs operation. in drive(1)mode, all dq, dq s (and rdqs) signals are driven high and all dqs (and rdqs ) signals are driven low. indrive(0) mode, all dq, dqs (and rdqs) signals are driven low and all dqs (and rdqs ) signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characterist ics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions.output driver characteristics for ocd calibration default are specified in the following table. ocd applies only to normal full strength output drive setting defined by emr(1) and if half strength is set, ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable. after ocd calibrati on is completed or driver strength is set to default, subsequent emrs(1) commands not intended to adjust ocd characteristics must specify a[9:7] as?000? in order to maintain the default or calibrated value. ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs(1) command along with a 4 bit burst code to ddr2 sdram as in the following table. for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. dt0 in the table means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, all dqs of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step within the maximum step count range. when adjust mode command is issued, al from previously set value must be applied. table 9 off chip driver program a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive(1) dq, dqs, (rdqs) high and dqs (rdqs ) low 0 1 0 drive(0) dq, dqs, (rdqs) low and dqs (rdqs ) high 1 0 0 adjust mode 1 1 1 ocd calibration default table 10 off-chip-driv er adjust program 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0 000nop (no operation) nop (no operation) 0 001increase by 1 step nop 0 010decrease by 1 step nop 0 100nop increase by 1 step 1 000nop decrease by 1 step 0 101increase by 1 step increase by 1 step 0 110decrease by 1 step increase by 1 step 1 001increase by 1 step decrease by 1 step 1 010decrease by 1 step decrease by 1 step other combinations illegal
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 30 rev. 1.02, 2004-11 09112003-7yzf-nh5g for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds / t dh should be met as shown in figure 10 . input data pattern for adjustment, dt[0:3] is fixed and not affected by mrs addressing mode (i.e. sequential or interleave). figure 10 timing diagram adjust mode drive mode both drive(1) and drive(0), is used for controllers to measure ddr2 sdram driver impedance before ocd impedance adjustment. in this mode, all outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command. see figure 11 . figure 11 timing diagram drive mode nop nop nop nop nop emrs(1) cmd dq_in nop twr dqs_in ck, ck wl emrs(1) nop dm dqs ocd adjust mode ocd calibration mode exit tds tdh dt0 dt1 dt2 dt3 ocd1 nop nop nop nop emrs(1) cmd dq_in nop dqs_in ck, ck emrs(1) nop enter drive mode ocd calibration mode exit nop dqs high & dqs low for drive(1), dqs low & dqs high for drive 0 dqs high for drive(0) dqs high for drive(1) toit toit
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 31 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.4 on-die termination (odt) on-die terminatio n (odt) is a new feature on ddr2 components that allows a dram to turn on/off termi- nation resistance for each dq, dqs, dqs , dm for 4 and dq, dqs, dqs , dm, rdqs (dm/rdqs share the same pin) and rdqs for 8 configuration via the odt control pin. dqs and rdqs are only terminated when enabled by emr(1). for 16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. udqs and ldqs are terminated only when enabled in the emrs(1) by address bit a10 = 0. the odt feature is designed to improve signal integ- rity of the memory channel by allowing the dram con- troller to independently turn on/off termination resis- tance for any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self-refresh mode. figure 12 functional representation of odt switch sw1 or sw2 is enabled by the odt pin. selection between sw1 or sw2 is determined by ?rtt (nominal)? in emrs(1) address bits a6 & a2. target: rval1 = rval2 = 2 rtt the odt pin will be igno red if the extended mode register (emrs(1)) is programmed to disable odt. odt timing modes depending on the operating mode asynchronous or synchronous odt timings apply. asynchronous odt timings ( t aofpd , t aonpd ) apply when the on-die dll is disabled. these modes are: slow exit active power down mode (with mrs bit a12 is set to ?1?) precharge power down mode synchronous odt timings ( t aond , t aofd , t aon , t aof ) apply for all other modes. dram input buffer input pin rval1 rval1 rval2 rval2 sw1 sw1 sw2 sw2 vddq vddq vssq vssq
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 32 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 13 odt timing for active and standby (idle) modes (synchronous odt timings) note 1. synchronous odt timings apply for active mode and standby mode with cke high and for the ?fast exit? active power down mode (mrs bit a12 set to ?0?). in all thes e modes the on-die dll is enabled. 2. odt turn-on time ( t aon,min ) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max. ( t aon,max ) is when the odt resistance is fully on. both are measured from t a ond . 3. odt turn off time min. ( t aof,min ) is when the device starts to turn off the odt resistance.odt turn off time max. ( t aof,max ) is when the bus is in high impedance. both are measured from t aofd . figure 14 odt timing for precharge power-down and active power-down mode (with slow exit) (asynchronous odt timings) note: asynchronous odt timings apply for precharge po wer-down mode and ?slow exit? active power down mode (mrs bit a12 set to ?1?), where the on-die dll is disabled in this mode of operation. cke dq odt01 odt ck, ck rtt taon(min) taon(max) taof(max) taof(min) taond (2 tck) taofd (2.5 tck) t is t is t0 t1 t2 t3 t4 t5 t6 t7 t8 is t taofpdmax cke dq odt odt02 ck, ck "low" t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t is t is rtt taonpd,min taofpdmin taonpd,max
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 33 rev. 1.02, 2004-11 09112003-7yzf-nh5g odt timing mode switch when entering the power down modes ?slow exit? active power down and precharge power down two additional timing parameters ( t anpd and t axpd ) define if synchronous or asynchronous odt timings have to be applied. mode entry as long as the timing parameter t anpd,min is satisfied when odt is turned on or off before entering these power-down modes, synchronous timing parameters can be applied. if t anpd,min is not satisfied, asynchronous timing parameters apply. figure 15 odt mode entry timing diagram cke ck, ck tanpd (3 tck) t0 t1 t2 t-1 t-2 t-3 t-4 t-5 t is odt03 odt turn-off, tanpd >= 3 tck : odt turn-off, tanpd <3 tck : taofd rtt odt t is rtt t is odt taond rtt taonpdmax odt odt turn-on, tanpd >= 3 tck : synchronous timings apply synchronous timings apply asynchronous timings apply taofpdmax odt rtt asynchronous timings apply odt turn-on, tanpd < 3 tck : t is
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 34 rev. 1.02, 2004-11 09112003-7yzf-nh5g mode exit as long as the timing parameter t axpd,min is satisfied when odt is turned on or off after exiting these power- down modes, synchronous timing parameters can be applied. if t axpd, min is not satisfied, asynchronous timing parameters apply. figure 16 odt mode exit timing diagram 2.5 bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank addresses ba[2:0] are used to select the desired bank. the row addresses a0 through a13 are used to determine which row to activate in the selected bank for 4 and 8 organized components. for 16 components row addresses a0 through a12 have to be applied. the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command (with or without auto-precharge) on the following clock cycle. if a r/w command is issued to a bank that has not satisfied the t rcd,min specification, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcd,min is satisfied. additive latencies of 0, 1, 2, 3 and 4 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , cke taxpd odt04 odt turn-off, taxpd >= taxpdmin: rtt rtt taonpdmax t0 t1 t5 t6 t7 t8 t is synchronous timings apply t9 odt turn-off, taxpd < taxpdmin: asynchronous timings apply odt taofd rtt odt taofpdmax rtt odt turn-on, taxpd >= taxpdmin: synchronous timings apply taond t is t is odt t is odt t is odt turn-on, taxpd < taxpdmin: asynchronous timings apply t10 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 35 rev. 1.02, 2004-11 09112003-7yzf-nh5g respectively. the minimum time interval between successive bank activate commands to the same bank is determined by t rc . the minimum time interval between bank active commands to different banks is t rrd . in order to ensure that components with 8 internal memory banks do not exceed the instantaneous current supplying capability, certain restrictions on operation of the 8 banks must be observed. there are two rules. one for restricting the number of sequential active commands that can be issued and another for allowing more time for ras precharge for a precharge-all command. the rules are as follows: 1. sequential bank activation restriction: no more than 4 banks may be activated in a rolling t faw window. converting to cloc ks is done by dividing t faw(ns) by t ck(ns) and rounding up to next integer value. as an example of the rolling window, if ( t faw / t ck ) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clocks n + 1 through n + 9. 2. precharge all allowance: t rp for a precharge-all command must be increased by 1 t ck . figure 17 bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2 2.6 read and write commands and access modes after a bank has been activa ted, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clock?s rising edge. we must also be defined at this time to determine whether the access cycle is a read operation (we high) or a write operation (we low). the ddr2 sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles at data rates of up to 533 mb/sec/pin for main memory. the boundary of the burst cycle is restricted to specific segments of the page length. for example, the 64mbit 16 chip has a page size of 2048 kbyte which corresponds to a page length of 1024 bits (defined by ca[9:0]). in case of a 4-bit burst operation (burst length = 4) the page length of 1024 is divided into 256 uniquely addressable segments (4-bits 16 i/o each). the 4-bit burst operation will occur entirely within one of the 256 segments (defined by ca[7:0]) starting with the column address supplied to the device during the read or write command (ca[9:0]). the second, third and fourth access will also occur within this segment, however, the burst order is a function of the starting address, and the burst sequence. in case of a 8-bit burst operation (burst length = 8) the page length of 1024 is divided into 128 uniquely addressable segments (8-bits 16 i/o each). the 8-bit burst operation will occur entirely within one of the 128 segments (defined by ca[6:0]) beginning with the column address supplied to the device during the read or write command (ca[9:0]). a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. therefore the minimum cas to cas delay ( t ccd ) is a minimum of 2 clocks for read or write cycles. address nop command t0 t2 t1 t3 t4 col. addr. bank a row addr. bank b col. addr. bank b internal ras-cas delay trcdmin. bank a to bank b delay trrd. activate bank b read a posted cas activate bank a read b posted cas read a begins row addr. bank a addr. bank a precharge bank a nop addr. bank b precharge bank b row addr. bank a activate bank a trp row precharge time (bank a) trc row cycle time (bank a) tn tn+1 tn+2 tn+3 act tras row active time (bank a) additive latency al=2 ck, ck tccd
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 36 rev. 1.02, 2004-11 09112003-7yzf-nh5g for 8 bit burst operation (bl = 8) the minimum cas to cas delay ( t ccd ) is 4 clocks for read or write cycles. burst interruption is allowed with 8 bit burst operation. for details see chapter 2.6.6 . figure 18 read burst timing example: (c l = 3, al = 0, rl = 3, bl = 4) 2.6.1 posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immediately after the bank activate command (or any time during the ras to cas delay time, t rcd period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the t rcd,min , then al greater than 0 must be written into the emr(1). the write latency (wl) is always defined as rl - 1 (read latency -1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcd,min period, the read latency is also defined as rl = al + cl. figure 19 activate to read timing example: read followed by a write to the same bank, activate to read delay < t rcdmin : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 4 nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t12 cmd dq rb dq s, dq s read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout c0 dout c1 dout c2 dout c3 nop read c tccd tccd ck, ck activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 dout0 dout1 dout2dout3 din0 din1 din2 din3 bank a read write bank a
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 37 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 20 read to write timing example: read followed by a write to the same bank, activate to read delay < t rcdmin : al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl -1) = 4, bl = 8 figure 21 read to write timing example: read followed by a write to the same bank, activate to read delay = t rcdmin : al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl -1) = 2, bl = 4 figure 22 read to write timing example: read followed by a write to the same bank, activate to read delay > t rcdmin : al = 1, cl = 3, rl = 4, wl = 3, bl = 4 activate bank a trcd cl = 3 al = 2 rl = al + cl = 5 wl = rl -1 = 4 postcas3 cmd dq dqs, dqs ck, ck 02345 1 6 7 8 9 10 11 bank a read write bank a din0 din1 din2 din3 dout0 dout1dout2 dout3 dout4 dout5 dout6 dout7 12 activate bank a bank a write trcd cl = 3 al = 0 rl = al + cl = 3 wl = rl -1 = 2 postcas2 bank a cmd dq dqs, dqs ck, ck 02345 1 67891011 read dout0 dout1 dout2 dout3 din0 din1 din2 din3 activate bank a trcd > trcdmin. rl = 4 wl = 3 postcas5 cmd dq dqs, dqs ck, ck 0 2 34 5 1 67891011 bank a read dout0 dout1 dout2 dout3 din0 din1 din2 din3 write bank a 12 13
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 38 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.6.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by the addresses a[2:0] of the mr. the burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (a3) of the mr. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the chapter 2.6.6 . a burst stop command is not supported on ddr2 sdram devices. note 1. page size and length is a function of i/o organization: ?256mb 4 organization (ca[9:0], ca11); page size = 1 kbyte; page length = 2048 ?128mb 8 organization (ca[9:0]); page size = 1 kbyte; page length = 1024 ?64mb 16 organization (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble-based? and therefore different from sdr or ddr components 2.6.3 read command the read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data-out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs(1)). table 11 burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 0 1 1, 2, 3, 0 1, 0, 3, 2 0 1 0 2, 3, 0, 1 2, 3, 0, 1 0 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 39 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 23 basic read timing diagram figure 24 burst operation example 1: rl = 5 (al = 2, cl = 3, bl = 4) dqs, dqs dq dqs dqs t rpre t dqsqmax t rpst t dqsck t ac dout dout dout dout clk, clk clk clk t ch t cl t ck do-read t qh dqsqmax t qh t t lz t hz nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= t dqsck cmd dq bread523 dqs, dqs posted cas ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 40 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 25 read operation example 2: rl = 3 (al = 0, cl = 3, bl = 8) figure 26 read followed by write example: rl = 5, wl = (rl-1) = 4, bl = 4 the minimum time from the read command to the write command is defined by a read-to-write turn-around time, which is bl/2 + 2 clocks. cmd nop nop nop nop nop nop dq's nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= tdqsck bread303 dq s, dq s dout a4 dout a5 dout a6 dout a7 ck, ck nop posted cas write a nop nop nop nop nop read a posted cas t0 t1 dout a0 dout a1 dout a2 dout a3 rl = 5 nop cmd dq brbw514 t3 t4 t5 t6 t7 t8 t9 din a0 din a1 din a2 din a3 dq s, dq s wl = rl - 1 = 4 bl/2 + 2 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 41 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 27 seamless read operation example 1: rl = 5, al = 2, cl = 3, bl = 4 the seamless read operation is supported by enabling a read command at every bl / 2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. figure 28 seamless read operation example 2: rl = 3, al = 0, cl = 3, bl = 8 (non interrupting) the seamless, non interrupting 8-bit read operation is supported by enabling a read command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. 2.6.4 write command the write command is in itiated by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl - 1). a data strobe signal (dqs) has to be driven low (preamble) a time t wpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss specification must be satisfied for write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed. when the burst has finished, any additional data supplied to the dq pi ns will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is named ?write recovery time? ( t wr ) and is the time needed to store the write data into the memory array. t wr is an analog timing parameter (see chapter 5 ) and is not the programmed value for wr in the mrs. nop nop nop nop nop nop nop read a posted cas read b posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dqs, dqs ck, ck nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout a4 dout a5 dout a6 dout a7 rl = 3 cl = 3 sbr_bl8 cmd dq dqs, dqs read b posted cas dout b0 dout b1 dout b2 dout b3 dout b4 nop nop nop nop nop t9 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 42 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 29 basic write timing figure 30 write operation example 1: rl = 5 (al = 2, cl = 3), wl = 4, bl = 4 figure 31 write operation example 2: rl = 3 (al = 0, cl = 3), wl = 2, bl = 4 dqs, dqs dqs dqs t dqsh t dqsl t wpre wpst t din din din din t ds t dh nop nop nop nop nop precharge nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= t dqss twr completion of the burst write dqs, dqs ck, ck nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 bw322 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write <= t dqss precharge bank a activate trp dqs, dqs ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 43 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 32 write followed by read example: rl = 5 (al = 2, cl = 3), wl = 4, t wtr = 2, bl = 4 the minimum number of clocks from the write command to the read command is (cl - 1) +bl/2 + t wtr , where t wtr is the write-to-read turn-around time t wtr expressed in clock cycles. the t wtr is not a write recovery time ( t wr ) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the array. figure 33 seamless write operation example 1: rl = 5, wl = 4, bl = 4 the seamless write operation is supported by enabling a write command every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. nop nop nop nop nop read a posted cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop twtr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 write to read = (cl - 1)+ bl/2 +twtr(2) = 6 dqs, dqs wl = rl - 1 = 4 rl=5 ck, ck nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a posted cas wl = rl - 1 = 4 write b posted cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dqs, dqs ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 44 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 34 seamless write operation example 2: rl = 3, wl = 2, bl = 8, non interrupting the seamless, non interrupting 8-bit burst write operation is supported by enabling a write command at every bl/2 number of clocks. this operation is allowed regardless of same or different banks as long as the banks are activated. 2.6.5 write data mask one write data mask input (dm) for 4 and 8 components and two write data mask inputs (ldm, udm) for 16 components ar e supported on ddr2 sdram?s, consistent with the implementation on ddr sdram?s. it has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. data mask is not used during read cycles. if dm is high during a write burst coincident with the write data, the write data bit is not written to the memory. for 8 components the dm function is disabled, when rdqs / rdqs are enabled by emrs(1). figure 35 write data mask timing nop nop nop nop nop nop nop write a wl = rl - 1 = 2 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbw_bl8 dq s, dq s write b din a0 din a1 din a2 din a3 din a4 din a5 din a5 din a7 din b0 din b1 din b2 din b3 din b4 din b5 din b6 din b7 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 45 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 36 write operation with data mask example: rl = 3 (al = 0, cl = 3), wl = 2, t wr = 3, bl = 4 2.6.6 burst interruption interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. a read burst can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst can only be interrupted by another write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 5. read or write burst inte rruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto-precharge enabled is not allowed to be interrupted. 7. read burst interruption is allowed by a read with auto-precharge command. 8. write burst interruption is allowed by a write with auto-precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un-interrupted burst end and not form the end of the actual burst end. nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 dm cmd dq nop tw r <= tdqss precharge bank a a ctivate tr p dq s, dq s dm din a0 din a1 din a3 din a2 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 46 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 37 read interrupt timing example 1: (cl = 3, al = 0, rl = 3, bl = 8) figure 38 write interrupt timing example 2: (cl = 3, al = 0, wl = 2, bl = 8) nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b7 nop ck, ck nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dq s, dq s nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 nop write b ck, ck nop
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 47 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.7 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre-charge command can be used to precharge each bank independently or all banks simultaneously. 4 address bits a10, ba[2:0] are used to define which bank to precharge when the command is issued. note: the bank address assignment is the same for activating and precharging a specific bank. 2.7.1 read operation followed by a precharge the following rules apply as long as the t rtp timing parameter - internal read to precharge command delay time - is less or equal two clocks, which is the case for operating frequencies less or equal 266 mhz (ddr2 400 and 533 speed sorts). minimum read to precharge command spacing to the same bank = al + bl/2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is ?additive latency (al) + bl/2 clocks? after a read command, as long as the minimum t ras timing is satisfied. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the precharge begins. 2. the ras cycle time ( t rc,min ) from the previous bank activation has been satisfied. table 12 bank selection for precharge by address bits a10 ba2 ba1 ba0 precharge bank(s) 0 0 0 0 bank 0 only 0 0 0 1 bank 1 only 0 0 1 0 bank 2 only 0 0 1 1 bank 3 only 0 1 0 0 bank 4 only 0 1 0 1 bank 5 only 0 1 1 0 bank 6 only 0 1 1 1 bank 7 only 1 don?t care don?t care don?t care all banks
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 48 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 39 read operation followed by precharge example 1: rl = 4 (al = 1, cl = 3), bl = 4, t rtp 2clocks figure 40 read operation followed by precharge example 2: rl = 4 (al = 1, cl = 3), bl = 8, t rtp 2clocks nop precharge nop bank a activate nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp ck, ck nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p413(8) nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 1 cl = 3 rl = 4 >=tras cl = 3 trp dqs, dqs nop >=trc >=trtp dout a4 dout a5 dout a6 dout a7 precharge nop bank a activate first 4-bit prefetch second 4-bit prefetch ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 49 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 41 read operation followed by precharge example 3: rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2clocks figure 42 read operation followed by precharge example 4: rl = 6, (al = 2, cl = 4), bl = 4, t rtp 2clocks nop nop nop bank a activate nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p523 nop al + bl/2 clks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 3 rl = 5 >=tras cl = 3 trp precharge dqs, dqs >=trc >=trtp ck, ck nop nop nop read a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq br-p624 nop al + bl/2 clocks dout a0 dout a1 dout a2 dout a3 al = 2 cl = 4 rl = 6 >=tras cl = 4 trp precharge a bank a activate dqs, dqs nop nop >=trc >=trtp ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 50 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.7.2 write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. this delay is know n as a write recovery time ( t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see chapter 7 ) and is not the programmed value wr in the mr. figure 43 write followed by precharge example 1: wl = (rl - 1) = 3, bl = 4, t wr = 3 figure 44 write followed by precharge example 2: wl = (rl - 1) = 4, bl = 4, t wr = 3 nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 wl = 3 bw-p3 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck nop nop nop nop nop write a posted cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 51 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.8 auto-precharge operation before a new row in an active bank can be opened, the active bank must be precha rged using either the pre- charge command or the auto-precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto- precharge function is enabled. during auto-precharge, a read command will execut e as normal with the exception that the active ba nk will begin to precharge internally on the rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto- precharge is also implemented for write commands. the precharge operation engaged by the auto- precharge command will not b egin until the last data of the write burst sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lockout circ uit internally delays the precharge operation until the array restore operation has been completed so that the auto-precharge command may be issued with any read or write command. 2.8.1 read with auto-precharge if a10 is 1 when a read command is issued, the read with auto-precharge func tion is engaged. the ddr2 sdram starts an auto-precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras,min and t rtp are satisfied. if t ras,min is not satisfied at the edge, the start point of auto-precharge operation will be delayed until t ras,min is satisfied. if t rtp,min is not satisfied at the edge, the start point of auto-prechar ge operation will be delayed until t rtp,min is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto-precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto-precharge to the next activate command is al + 2 + t rtp + t rp . note that ( t rtp + t rp ) has to be rounded up to the next integer value. in any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. a new bank active command may be issued to the same bank if the following two conditions are satisfied simultaneously: 1. the ras precharge time ( t rp ) has been satisfied from the clock at which the auto-precharge begins. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 52 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 45 read with auto-precharge example 1, followed by an activation to the same bank ( t rc limit): rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 clocks figure 46 read with auto-precharge example 2, followed by an activation to the same bank ( t ras limit): rl = 5 (al = 2, cl = 3), bl = 4, t rtp 2 clocks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dq s, dq s tras trcmin. nop al + bl/2 ck, ck nop nop nop nop b ank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dq s, dq s trc tras(min) nop ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 53 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 47 read with auto-precharge example 3, followed by an activation to the same bank: rl = 4 (al = 1, cl = 3), bl = 8, t rtp 2 clocks nop nop nop nop bank a ctivate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dq s, dq s nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 54 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.8.2 write with auto-precharge if a10 is high when a write command is issued, the write with auto-precharge function is engaged. the ddr2 sdram automatica lly begins precharge operation after the completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto-precharge from the completion of the write burst may be reacti vated if the following two conditions are satisfied. 1. the last data-in to bank activate delay time ( t dal = wr + t rp ) has been satisfied. 2. the ras cycle time ( t rc ) from the previous bank activation has been satisfied. in ddr2 sdram?s the write recovery time delay (wr) has to be programmed into the mrs mode register. as long as the analog t wr timing parameter is not violated, wr can be programmed between 2 and 6 clock cycles. minimum write to activate command spacing to the same bank = wl + bl/2 + t dal . figure 48 write with auto-precharge example 1 ( t rc limit): wl = 2, t dal = 6 (wr = 3, t rp = 3), bl = 4 figure 49 write with auto-precharge example 2 (wr + t rp limit): wl = 4, t dal = 6 (wr = 3, t rp = 3), bl = 4 nop nop nop nop nop bank a a ctivate nop write w /a p t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dq s, dq s completion of the burst write tdal >=trasmin. ck, ck nop nop nop nop nop bank a a ctivate nop write w/ap posted cas t0 t3 t4 t5 t6 t7 t12 nop cmd dq bw-ap423 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 4 wr >=trc t9 t8 completion of the burst write dq s, dq s tdal >=tras ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 55 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.8.3 read or write to precharge command spacing summary the following table summarizes the minimum command delays between read, read w/ap, write, write w/ap to the precharge commands to the same banks and precharge-all commands. table 13 minimum command delays from command to command minimum delay between ?from command? to ?to command? unit note read precharge (to same banks as read) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) 1) ru{ t rtp (ns) / t ck (ns)} must be used, where ru stands for ?round up? 2) for a given bank, the precharge period shoul d be counted from the latest precharge co mmand, either one bank precharge or precha rge- all, issued to that bank. the pr echarge period is satisfied after t rp or t rpa depending on the latest precharge command issued to that bank precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) read w/ap precharge (to same banks as read w/ap) al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) precharge-all al + bl/2 + max( t rtp , 2) - 2 t ck t ck 1)2) write precharge (to same banks as write) wl + bl/2 + t wr t ck 2)3) 3) ru{ t wr (ns) / t ck (ns)} must be used, where ru stands for ?round up? precharge-all wl + bl/2 + t wr t ck 2)3) write w/ap precharge (to same banks as write w/ap) wl + bl/2 + wr t ck 2) precharge-all wl + bl/2 + wr t ck 2) precharge precharge (to same banks as precharge) 1 t ck 2) precharge-all 1 t ck 2) precharge-all precharge 1 t ck 2) precharge-all 1 t ck 2)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 56 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.8.4 concurrent auto-precharge ddr2 devices support the ?concurrent auto- precharge? feature. a read with auto-precharge enabled, or a write with auto-precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the read or write data transfer, and all other related limitations (e.g. contention between read data and write data must be avoided externally and on the internal data bus). the minimum delay from a read or write command with auto-precharge enabled, to a command to a different bank, is summarized in table 14 . as defined, the wl = rl - 1 for ddr2 devices which allows the command gap and corresponding data gaps to be minimized. 2.9 refresh ddr2 sdram requires a refresh of all rows in any rolling 64 ms interval. the necessary refresh can be generated in one of two ways: by explicit auto-refresh comma nds or by an internally timed self-refresh mode. 2.9.1 auto-refresh command auto-refresh is used during normal operation of the ddr2 sdram?s. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto-refresh command. the ddr2 sdram requires auto-refresh cycles at an average periodic interval of t refi(maximum) . when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto- refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time ( t rp ) before the auto-refresh command can be applied. an internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharge d (idle) state. a delay between the auto-refresh command and the next activate command or subsequent auto-refresh command must be greater than or equal to the auto- refresh cycle time ( t rfc ). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 t refi . table 14 command delay table from command to command (different bank, non-interrupting command) minimum delay with concurrent auto- precharge support unit note write w/ap read or read w/ap (cl -1) + (bl/2) + t wtr t ck 1) 1) ru{t wtr (ns)/t ck (ns)} must be used where ru stands for ?round up? write or write w/ap bl/2 t ck precharge or activate 1 t ck 2) 2) this rule only applies to a selective precharge comm and to another bank, a precharge-all command is illegal read w/ap read or read w/ap bl/2 t ck write or write w/ap bl/2 + 2 t ck precharge or activate 1 t ck 2)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 57 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 50 auto refresh timing 2.9.2 self-refresh command the self-refresh command can be used to retain data, even if the rest of the system is powered down. when in the self-refresh mode, the ddr2 sdram retains data without external clocking. the ddr2 sdram device has a built-in timer to accommodate self- refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. the device must be in idle state and odt must be turned off before issuing self refresh command, by either driving odt pin low or using emrs(1) command. once the command is registered, cke must be held low to keep the device in self-refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self-refresh mode all of the external control signals, except cke, are ?don?t care?. the dram initiates a minimum of one auto refresh command internally within t cke period once it enters self refresh mode. the clock is internally disabled during self-refresh operation to save power. the minimum time that the ddr2 sdram must remain in self refresh mode is t cke . the user may change the external clock frequency or halt the external clock one clock after self-refresh entry is registered, however, the clock must be restarted and stable before the device can exit self-refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back h igh. once self-refresh exit command is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for th e entire self-refresh exit period t xsrd for proper operation. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after t xsnr expires. nop or deselect commands must be registered on each positive clock edge during the self-refresh exit interval t xsnr . odt should be turned off during t xsnr . the use of self refresh mo de introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop a u to refresh any nop > = t rfc > = t rfc a u to refresh nop nop nop cke "high"
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 58 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 51 self refresh timing note 1. device must be in the ?all banks idle? state before entering self refresh mode. 2. t xsrd ( 200 t ck ) has to be satisfied for a read or a read with auto-precharge command. 3. t xsnr has to be satisfied for any command except a read or a read with auto-precharge command 4. since cke is an sstl input, v ref must be maintained during self refresh. 2.10 power-down power-down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge, auto-precharge or auto-refresh is in progress, but power-down i dd specification will not be applied until finishing those operations. the dll should be in a locked state when power-down is entered. otherwise dll should be reset after exiting power-down mode for proper read operation. dram design guarantees it?s dll in a locked state with any cke intensive operations as long as dram controller complies with dram specifications. if power-down occurs when all banks are precharged, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. for active power-down two different power saving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as ?standard active power-down mode? and a fast power-down exit timing defined by the t xard timing parameter can be used. when a12 is set to high this mode is referred as a power saving ?low power active power-down mode?. this mode takes longer to exit from the power-down mode and the t xards timing parameter has to be satisfied. entering power-down deactivates the input and output buffers, excluding ck, ck , odt and cke. also the dll is disabled upon entering precharge power-down or slow exit active power-d own, but the dll is kept enabled during fast exit active power-down. in power- down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and all other input signals are ?don?t care?. power-down duration is limited by 9 times t refi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid, executable command can be applied with power-down exit latency, t xp , t xard or t xards , after cke goes high. power-down exit latencies are defined in table 42 . ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr tn tr tm t5 t4 trp tis taofd cmd self refresh entry nop non-read command read command t0 tis tis odt tcke
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 59 rev. 1.02, 2004-11 09112003-7yzf-nh5g power-down entry active power-down mode can be entered after an activate command. precharge power-down mode can be entered after a precharge, precharge-all or internal precharge command. it is also allowed to enter power- mode after an auto-refresh command or mrs / emrs(1) command when t mrd is satisfied. active power-down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power-down mode entry after a read or read with auto-precharge command is allowed after rl + bl/2 is satisfied. active power-down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active power- down mode entry is allowed when wl + bl/2 + t wtr is satisfied. in case of a write command with auto-precharge, power-down mode entry is allowed after the internal precharge command has been executed, which is wl + bl/2 + wr starting from the write with auto- precharge command. in this case the ddr2 sdram enters the precharge power-down mode. figure 52 active power-down mode entry and exit after an activate command note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. nop nop activate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit v alid command txard or txards *) ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 60 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 53 active power-down mode entry and exit example after a read command: rl = 4 (al = 1, cl =3), bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. figure 54 active power-down mode entry and exit example after a write command: wl = 2, t wtr =2,bl= 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit v alid command txard or txards *) ck, ck read w/ap nop nop write t0 t2 t1 t3 t4 t5 t6 t7 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 wl + bl/2 + twtr nop nop act.pd 2 twtr tis tn+2 tis v alid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 active power-down entry
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 61 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 55 active power-down mode entry and exit example after a write command with ap: wl = 2, wr = 3, bl = 4 note: active power-down mode exit timing t xard (?fast exit?) or t xards (?slow exit?) depends on the programmed state in the mr, address bit a12. wr is the programmed value in the mrs mode register. figure 56 precharge power down mode entry and exit note: "precharge" may be an external command or an internal precharge following write with ap. nop nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 cmd dq d q s, d q s nop nop nop nop nop nop tn tn+1 cke wl = rl - 1 = 2 wl + bl/2 + wr nop nop act.pd 3 wr tis tn+2 tis v alid command active power-down exit txard or txards *) ck, ck din a0 din a1 din a2 din a3 active power-down entry txp nop nop precharge t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop tis tn+2 tis precharge power-down exit valid command trp nop t3 ck, ck
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 62 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 57 auto-refresh command to power-down entry figure 58 mrs, emrs command to power-down entry t0 t2 t1 t3 t4 tn cmd cke ck, ck auto refresh arpd trfc tis txp valid command cke can go low one clock after an auto-refresh command when trfc expires the dram is in precharge power-down mode t0 t2 t1 t3 t4 t5 t6 t7 cmd cke ck, ck mrs or emrs mrs_pd t mrd enters precharge power-down mode
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 63 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.11 other commands 2.11.1 no operation command the no operation command (nop) should be used in cases when the sdram is in a idle or a wait state. the purpose of the no operation command is to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will no t terminate a previous operation that is still executin g, such as a burst read or write cycle. 2.11.2 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t care. 2.12 input clock frequency change during operation the dram input clock frequency can be changed under the following conditions: during self-refresh operation dram is in precharge power-down mode and odt is completely turned off. in the latter case the ddr2-sdram has to be in precharged power-down mode and idle. odt must be already turned off and cke must be at a logic low state. after a minimum of two clock cycles after t rp and t aofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can be changed to a high logic level again. after t xp has been satisfied a dll reset command via emrs(1) has to be issued. during the following dll re-lock period of 200 clock cycles, odt must remain off. after the dll-re-lock period the dram is ready to operate with the new clock frequency. figure 59 input frequency change example during precharge power-down mode nop nop t0 t2 t1 t3 t4 tx tx+1 ty cmd nop nop nop nop nop dll reset ty+2 ty+3 cke frequency change occurs here nop nop frequ.ch. tz txp stable new clock before power-down exit ck, ck trp taofd minimum 2 clocks required before changing the frequency ty+1 nop v alid command 200 clocks odt is off during dll reset
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram functional description data sheet 64 rev. 1.02, 2004-11 09112003-7yzf-nh5g 2.13 asynchronous cke low reset event in a given system, asynch ronous reset event can occur at any time without prior knowledge. in this situation, memory controller is forced to drop cke asynchronously low, immediately interrupting any valid operation. dram requ ires cke to be maintained high for all valid operations as defined in this data sheet. if cke asynchronously drops low during any valid operation, the dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised high again. the dram must be fully re-initialized as described the initialization sequence ( chapter 2.2.1 , step 4 through 13). dram is ready for normal operation after the initialization sequence. see chapter 7 for t delay specification. figure 60 asynchronous low reset event cke cke drops low due to an asynchronous reset event clocks can be turned off after this point tdelay ck, ck stable clocks
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram truth tables data sheet 65 rev. 1.02, 2004-11 09112003-7yzf-nh5g 3 truth tables table 15 command truth table function cke cs ras cas we ba0 ba1 ba2 a[13:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the stat es described in this table. the odt functi on is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before no rmal operation can continue. previous cycle current cycle (extended) mode register set h h l l l l ba op code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 5) bank addresses (bax) determine which bank is to be operated upon. for (e)mrs bax selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. see chapter 2.6.6 for details. write with auto- precharge h h l h l l ba column h column 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto- precharge h h l h l h ba column h column 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations . the duration of power down is therefore limited by the refresh requirements outlined in chapter 2.7 lh h h power down exit l h h x x x x x x x 4)9) lh h h
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram truth tables data sheet 66 rev. 1.02, 2004-11 09112003-7yzf-nh5g table 16 clock enable (cke) truth table for synchronous transitions current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2) 3) ras , cas , we , cs 2) command (n) is the command registered at clock edge n, and action (n) is a result of command (n) 3) the state of odt does not affect the stat es described in this table. the odt func tion is not available during self refresh. see chapter 2.4 . action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) v ref must be maintained during self refresh operation. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; cke (n-1) was the stat e of cke at the previous clock edge. current cycle 6) (n) power-down l l x mai ntain power-down 7)8)11) 7) the power-down mode does not perform an y refresh operations. the duration of po wer-down mode is therefor limited by the refresh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if t he odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 10) valid commands for power-down entr y and exit are nop and deselect only. 11) t ckemin of 3 clocks means cke must be register ed on three consecutive positive clock edges. cke must rema in at the valid input level the entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke transition, cke may not transition from its valid leve l during the time period of t is + 2 t cke + t ih . self refresh l l x main tain self refresh 8)11) l h deselect or nop self refresh exit 9)12)13) 12) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 13) valid commands for self refr esh exit are nop and deselct only. bank(s) active h l deselect or nop activ e power-down entry 7)9)10)11)14) 14) power-down and self refresh can not be entered while re ad or write operations, (extend ed) mode register operations, precharge or refresh operations are in progress. see chapter 2.10 and chapter 2.9.2 for a detailed list of restrictions. all banks idle h l deselect or nop precharge power-down entry 9)10)11)14) h l autorefresh self refresh entry 7)11)13)15) 15) self refresh mode can only be enter ed from the all banks idle state. any state other than listed above h h refer to the command truth table 16) 16) must be a legal command as defined in the command truth table. table 17 data mask (dm) truth table name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram absolute maximum ratings data sheet 67 rev. 1.02, 2004-11 09112003-7yzf-nh5g 4 absolute maximum ratings table 18 absolute maximum ratings symbol parameter rating unit note v dd voltage on v dd pin relative to v ss -1.0 to +2.3 v 1) 1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. v ddq voltage on v ddq pin relative to v ss -0.5 to +2.3 v 1) v ddl voltage on vddl pin relative to v ss -0.5 to +2.3 v 1) v in , v out voltage on any pin relative to v ss -0.5 to +2.3 v 1) t stg storage temperature -55 to +100 c 1)2) 2) storage temperature is the case surface te mperature on the center/top side of the dram.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 68 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5 electrical characteristics 5.1 dc characteristics table 19 dram component operating temperature range symbol parameter rating unit note t oper operating temperature 0 to 95 o c 1)2)3)4) 1) operating temperature is the case surface tem perature on the center / top side of the dram. 2) the operating temperature ran ge are the temperatures where all dram specif ication will be support ed. during operation, the dram case temperature must be maintained between 0 - 95 o c under all other spec ification parameters. 3) above 85 o c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) self-refresh period is hard-coded in t he chip and therefore it is imperative that the system ensures the dram is below 85 o c case temperature before initiating self-refresh operation. table 20 recommended dc operating conditions (sstl_18) symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1) 1) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1) v ddq supply voltage for output 1.7 1.8 1.9 v 1) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2)3) 2) the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 4) 4) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . table 21 odt dc electrical characteristics parameter / condition symbol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1 (eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i ( v ihac ) and i ( v ilac ) respectively. rtt(eff) = ( v ih(ac) ? v il(ac) ) /( i ( v ihac ) ? i ( v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2 (eff) 120 150 180 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage ( v m ) at test pin (midpoint) with no load: delta v m =((2 x v m / v ddq ) ? 1) x 100%
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 69 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.2 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or fa lling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and char acterization but not subject to production test. in single ended mode, the dqs (and rdqs ) signals are internally disabled and don?t care. table 22 input and output leakage currents symbol parameter / condition min. max. unit note i il input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v i ol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs , rdqs, rdqs are disabled and odt is turned off table 23 dc & ac logic input levels symbol parameter min. max. unit v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.250 v table 24 single-ended ac input test conditions symbol condition value unit note v ref input reference voltage 0.5 x v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing(max) input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac)min to v ref for rising edges and the range from v ref to v il(ac)max for falling edges as shown in figure 61 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 70 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 61 single-ended ac input test conditions diagram figure 62 differential dc and ac input and output logic levels diagram table 25 differential dc and ac input and output logic levels symbol parameter min. max. unit note v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac ) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which di fferential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which di fferential input signals must cross. v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss v swing(max) delta tr delta tf start of falling edge input timing start of rising edge input timing v ref - v il (ac) max delta tf falling slew = rising slew = v ih(ac) min - v delta tr ref crossing point vddq vssq vid vix or vox vtr vcp sstl18_3
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 71 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.3 output buffer characteristics table 26 sstl_18 output dc current drive symbol parameter sstl_18 unit note i oh output minimum source dc current ?13.4 ma 1)2) 1) v ddq = 1.7 v; v out = 1.42 v. ( v out ? v ddq ) / i oh must be less than 21 ohm for values of v out between v ddq and v ddq ? 280 mv. 2) the values of i oh(dc) and i ol(dc) are based on the conditions given in 1) and 3) . they are used to test drive current capability to ensure v ihmin . plus a noise margin and v ilmax minus a noise margin are delivered to an sstl_18 receiver. the actual current values are derived by shifting th e desired driver operating points along 21 ohm load line to define a convenient current for measurement. i ol output minimum sink dc current 13.4 ma 2)3) 3) v ddq = 1.7 v; v out = 280 mv. v out / i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. table 27 sstl_18 output ac test conditions symbol parameter sstl_18 unit note v oh minimum required output pull-up v tt + 0.603 v 1) 1) sstl_18 test load for v oh and vol is different from the referenced load described in chapter 8.1 . the sstl_18 test load has a 20 ohm series resistor additionally to the 25 ohm termination resistor into v tt . the sstl_18 definition assumes that 335 mv must be developed across the effectiv ely 25 ohm termination resistor (13.4 ma 25 ohm = 335 mv). with an additional series resistor of 20 ohm this translates in to a minimum requirement of 603 mv swing relative to v tt , at the ouput device (13.4 ma 45 ohm = 603 mv). v ol maximum required output pull-down v tt ? 0.603 v 1) v otr output timing measurement reference level 0.5 v ddq v table 28 ocd default characteristics symbol description min. nominal max. unit note ? output impedance 12.6 18 23.4 ohms 1)2) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) impedance measurement condition for output source dc current: v ddq = 1.7 v, v out = 1420 mv; ( v out ? v ddq ) / i oh must be less than 23.4 ohms for values of v out between v ddq and v ddq ? 280 mv. impedance measurement condition for output sink dc current: v ddq = 1.7 v; v out = ?280 mv; v out / i ol must be less than 23.4 ohms for values of v out between 0 v and 280 mv. ? pull-up / pull down mismatch 0 ? 4 ohms 1)2)3) 3) mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. ? output impedance step size for ocd calibration 0 ? 1.5 ohms 4) 4) this represents the step size when the ocd is nea r 18 ohms at nominal condi tions across all process parameters and represents only the dram uncertainty. a 0 ohm value (no calibration) can only be achieved if the ocd impedance is 18 0.75 ohms under nominal conditions. s out output slew rate 1.5 ? 5.0 v / ns 1)5)6)7)8) 5) slew rates according to chapter 8.2.1 v il(ac) to v ih(ac) with the load specified in figure 67 . 6) the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is verified by design and characterization but not subject to production test. 7) timing skew due to dram output slew rate mis-match between dqs / dqs and associated dq?s is included in t dqsq and t qhs specification.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 72 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.4 default output v-i characteristics ddr2 sdram output driver characteristics are defined for full strength default operation as selected by the emrs(1) bits a[9:7] =?111?. figure 63 and figure 64 show the driver characteristics graphically and the tables show the same data suitable for input into simulation tools. 8) dram output slew rate specification applies to 400 and 533 mt/s speed bins. table 29 full strength default pull-up driver characteristics voltage (v) pull-up driver current [ma] min. 1) 1) the driver characteristics eval uation conditions are minimum 95 c ( t case ), v ddq = 1.7 v, slow?slow process nominal default low 2) 2) the driver characteristics evaluation conditions are nominal default 25 c ( t case ), v ddq = 1.8 v, typical process nominal default high 2) max. 3) 3) the driver characteristics evaluati on conditions are maximum 0 c ( t case ). v ddq = 1.9 v, fast?fast process 0.2 ?8.5 ?11.1 ?11.8 ?15.9 0.3 ?12.1 ?16.0 ?17.0 ?23.8 0.4 ?14.7 ?20.3 ?22.2 ?31.8 0.5 ?16.4 ?24.0 ?27.5 ?39.7 0.6 ?17.8 ?27.2 ?32.4 ?47.7 0.7 ?18.6 ?29.8 ?36.9 ?55.0 0.8 ?19.0 ?31.9 ?40.8 ?62.3 0.9 ?19.3 ?33.4 ?44.5 ?69.4 1.0 ?19.7 ?34.6 ?47.7 ?75.3 1.1 ?19.9 ?35.5 ?50.4 ?80.5 1.2 ?20.0 ?36.2 ?52.5 ?84.6 1.3 ?20.1 ?36.8 ?54.2 ?87.7 1.4 ?20.2 ?37.2 ?55.9 ?90.8 1.5 ?20.3 ?37.7 ?57.1 ?92.9 1.6 ?20.4 ?38.0 ?58.4 ?94.9 1.7 ?20.6 ?38.4 ?59.6 ?97.0 1.8 ? ?38.6 ?60.8 ?99.1 1.9 ? ? ? ?101.1
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 73 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 63 full strength default pull-up driver diagram table 30 full strength default pull?down driver characteristics voltage (v) pull-down driver current [ma] min. 1) 1) the driver characteristics evaluation conditions are minimum 95 o c ( t case ), v ddq = 1.7 v, slow-slow process, nominal default low 2) 2) the driver characteristics evaluation conditions are nominal default 25 o c ( t case ), v ddq = 1.8 v, typical process, nominal default high 2) max. 3) 3) the driver characteristics eval uation conditions are maximum 0 o c ( t case ). v ddq = 1.9 v, fast-fast process 0.2 8.5 11.3 11.8 15.9 0.3 12.1 16.5 16.8 23.8 0.4 14.7 21.2 22.1 31.8 0.5 16.4 25.0 27.6 39.7 0.6 17.8 28.3 32.4 47.7 0.7 18.6 30.9 36.9 55.0 0.8 19.0 33.0 40.9 62.3 0.9 19.3 34.5 44.6 69.4 1.0 19.7 35.5 47.7 75.3 1.1 19.9 36.1 50.4 80.5 1.2 20.0 36.6 52.6 84.6 1.3 20.1 36.9 54.2 87.7 1.4 20.2 37.1 55.9 90.8 1.5 20.3 37.4 57.1 92.9 1.6 20.4 37.6 58.4 94.9 1.7 20.6 37.7 59.6 97.0 1.8 ? 37.9 60.9 99.1 1.9 ? ? ? 101.1 -120 -100 -80 -60 -40 -20 0 pullup current (ma) mi ni mum nominal def ault low nominal def ault high maxi mum
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 74 rev. 1.02, 2004-11 09112003-7yzf-nh5g t figure 64 full strength default pull?down driver diagram 5.4.1 calibrated output dr iver v-i characteristics ddr2 sdram output driver characteristics are defined for full strength calibrated o peration as selected by the procedure outlined in the off-chip driver (ocd) impedance adjustment. the table 31 and table 32 show the data in tabular format suitable for input into simulation tools. the nominal points represent a device at exactly 18 ohms. the nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohms step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). real system calibration error needs to be added to these values. it must be understood that these v-i curves are represented here or in supplier ibis models need to be adjusted to a wider range as a result of any system calibration error. since this is a system specific phenomena, it cannot be quantified here. the values in the calibrated tables represent just the dram portion of uncertainty while looking at one dq only. if the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figure. in such a situation, the timing parameters in the specification cannot be guaranteed. it is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. if this can?t be guaranteed by the system calibration procedure, re- calibration policy and unc ertainty with dq to dq variation, it is recommended that only the default values to be used. the nominal maximum ad minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. if calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. 0 20 40 60 80 100 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 vout to vssq (v) pulldown current (m a mi ni mum nominal def ault low nomi nal def aul t hi gh maxi mum
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 75 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.5 input / output capacitance table 31 full strength calibrated pu ll-down driver characteristics voltage (v) calibrated pull-down driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 o c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation conditions are nominal low and nominal high 25 o c ( t case ), v ddq = 1.8v, any process nominal 3) (18 ohms) 3) the driver characteristics eval uation conditions are nominal 25 o c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluati on conditions are nominal maximum 0 o c ( t case ), v ddq = 1.9 v, any process 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0 table 32 full strength calibrated pull-up driver characteristics voltage (v) calibrated pull-up driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 o c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics evaluation conditions are nominal low and nominal high 25 o c ( t case ), v ddq = 1.8v, any process nominal (18 ohms) 3) 3) the driver characteristics evalua tion conditions are nominal 25 o c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluati on conditions are nominal maximum 0 o c ( t case ), v ddq = 1.9 v, any process 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 table 33 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 1.0 2.0 pf cdi input capacitance delta, all other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs , rdqs, rdqs 2.5 4.0 pf cdio input/output capacitance delta, dq, dm, dqs, dqs , rdqs, rdqs ?0.5 pf
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 76 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.6 power & ground clamp v-i characteristics power and ground clamps are provided on address (a[13:0], ba[2:0]), ras , cas , cs , we , and odt pins. the v-i characteristics for pins with clamps is shown in table 34 . table 34 power & ground clamp v-i characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 77 rev. 1.02, 2004-11 09112003-7yzf-nh5g 5.7 overshoot and under shoot specification figure 65 ac overshoot / undershoot diagram for address and control pins figure 66 ac overshoot / undershoot diagram for clock, data, strobe and mask pins table 35 ac overshoot / undershoot specification for address and control pins parameter ddr2? 400 ddr2?533 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 v maximum overshoot area above v dd 0.75 0.56 v.ns maximum undershoot area below v ss 0.75 0.56 v.ns table 36 ac overshoot / undershoot specification for clock, data, strobe and mask pins parameter ddr2?400 ddr2?533 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 v maximum overshoot area above v ddq 0.38 0.28 v.ns maximum undershoot area below v ssq 0.38 0.28 v.ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram i dd specifications and conditions data sheet 78 rev. 1.02, 2004-11 09112003-7yzf-nh5g 6 i dd specifications and conditions table 37 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t rasmin(idd) , cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching . i dd0 1)2)3)4)5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t rasmin(idd) , t rcd = t rcd(idd) , al = 0, cl = c(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus i nputs are switching. i dd1 1)2)3)4)5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ; other control and address inputs are stable; data bus inputs are floating . i dd2p 1)2)3)4)5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching. i dd2n 1)2)3)4)5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4)5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3p(1) 1)2)3)4)5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t rasmax(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4)5)6) operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t rasmax.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4)5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t rasmax(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4)5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b 1)2)3)4)5)6) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d 1)2)3)4)5)6)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram i dd specifications and conditions data sheet 79 rev. 1.02, 2004-11 09112003-7yzf-nh5g self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. i dd6 1)2)3)4)5)6) all bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl=cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; t faw = t faw(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. 2. timing pattern for 4 and 8 components: ? ddr2-400: a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 (16 clocks) ? ddr2-533: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d (20 clocks) 3. timing pattern for 16 components: ? ddr2 -400: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d (20 clocks) ? ddr2 -533: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d (28 clocks) i dd7 1)2)3)4)5)6)7) 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : low is defined as v in v il(ac)max ; high is defined as v in v ih(ac)min ; stable is defined as inputs are stable at a high or low level; floating is defined as inputs are v ref = v ddq / 2; switching is defined as: inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes. 6) timing parameter minimum and maximum values for i dd current measurements are defined in table 40 . 7) a = activate, ra = read with auto-precharge, d=deselect table 37 i dd measurement conditions parameter symbol note
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram i dd specifications and conditions data sheet 80 rev. 1.02, 2004-11 09112003-7yzf-nh5g table 38 i dd specification product type speed code ?3.7 ?5 unit note speed grade ddr2?533 ddr2?400 symbol max. max. i dd0 75 70 ma 1) 1) 4/ 8 80 75 ma 2) 2) 16 i dd1 85 80 ma 1) 95 90 ma 2) i dd2p 55ma 3) 3) 16/ 4/ 8 i dd2n 46 35 ma 3) i dd2q 32 28 ma 3) i dd3p 17 13 ma 3)4) 4) mrs(12)=0 65ma 3)5) 5) mrs(12)=1 i dd3n 50 40 ma 3) i dd4r 110 90 ma 1) 130 105 ma 2) i dd4w 115 95 ma 1) 165 130 ma 2) i dd5b 185 180 ma 3) i dd5d 77ma 3) i dd6 55ma 3)6)7) 6) i dd6 : 0 t case 85 o c 7) standard products 33ma 3)8)9) 8) low power products 9) available on request i dd7 205 195 ma 1) 270 255 ma 2)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram i dd specifications and conditions data sheet 81 rev. 1.02, 2004-11 09112003-7yzf-nh5g 6.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: 6.2 on die termination (odt) current the odt function adds additional current consumption to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?weak? or ?strong? termination can be selected. the current consumption for any terminated input pin depends on whether the input pin is driven or floating. see table 40 . note: for power consumption calculations the odt duty cycle has to be taken into account table 39 i dd measurement test condition parameter symbol -3.7 -5 unit note ddr2?533 4?4?4 ddr2?400 3?3?3 cas latency cl (idd) 43 t ck clock cycle time t ck(idd) 3.75 5 ns active to read or write delay t rcd(idd) 15 15 ns active to active / auto-refresh command period t rc(idd) 60 55 ns four active window period t faw(idd) 37.537.5ns 1) 1) 4 & 8 (1 kb page size) 50 50 ns 2) 2) 16 (2 kb page size) active bank a to active bank b command delay t rrd(idd) 7.5 7.5 ns 1) 10 10 ns 2) active to precharge command t rasmin(idd) 45 40 ns t rasmax(idd) 70000 70000 ns precharge command period t rp(min) 15 15 ns auto-refresh to active / auto-refresh command period t rfc(idd) 127.5 127.5 ns table 40 odt current per terminated input pin odt current emrs(1) state min. typ. max. unit enabled odt current per dq added i ddq current for odt enabled; odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq active odt current per dq added i ddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 82 rev. 1.02, 2004-11 09112003-7yzf-nh5g 7 electrical characteristics table 41 speed grade definition speed bins speed grade ddr2?533c ddr2?400b unit note ifx sort name ?3.7 ?5 cas-rcd-rp latencies 4?4?4 3?3?3 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8 . timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) under the ?reference load for timing measurements? according to chapter 8.1 only. 2) the ck ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs ,rdqs/ rdqs , input reference level is the crosspoint when in di fferential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs , rdqs / rdqs is defined in chapter 8.3 . 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . see section 8 for the reference load for timing measurements. @ cl = 4 t ck 3.75 8 5 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 5 8 ns 1)2)3)4) ras-cas-delay t ras 45 70000 40 70000 ns 1)2)3)4)5) 5) t ras(max) is calculated from the maximum amount of time a dd r2 device can operate without a refresh command which is equal to 9 x t refi . row precharge time t rc 60 ? 55 ? ns 1)2)3)4) row active time t rcd 15 ? 15 ? ns 1)2)3)4) row cycle time t rp 15 ? 15 ? ns 1)2)3)4) table 42 timing parameter by sp eed grade - ddr2-400 & ddr2-533 parameter symbol ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 unit note 1)2)3)4)5)6) min. max. min. max. dq output access time from ck / ck t ac ?500 +500 ?600 + 600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge wr ite recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7) minimum time clocks remain on after cke asynch ronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?ns 8) dq and dm input hold time t dh (base) 225 ?? 275 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? 25 ? ps 9)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 83 rev. 1.02, 2004-11 09112003-7yzf-nh5g dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 +450 ?500 + 500 ps dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ? 350 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time t ds (base) 100 ? 150 ? ps 9) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? 25 ? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck four activate window period t faw 37.5 ? 37.5 ? ns 11)12) 50 ? 50 ? ns 13)12) clock half period t hp min. ( t cl, t ch) min. ( t cl, t ch) 14) data-out high-impedance time from ck / ck t hz ? t acmax ? t acmax ps 15) address and control input hold time t ih 375 ? 475 ? ps 9) address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck address and control input setup time t is 250 ? 350 ? ps 9) dq low-impedance time from ck / ck t lz(dq) 2 t acmin t acmax 2 t acmin t acmax ps 15) dqs low-impedance from ck / ck t lz(dqs) t acmin t acmax t acmin t acmax ps 15) mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 0 12 0 12 ns data output hold time from dqs t qh t hp - t qhs ? t hp- t qhs ? data hold skew factor t qhs ? 400 ? 450 ps average periodic refresh interval t refi ?7.8?7.8 s 16)17) ?3.9?3.9 s 16)18) auto-refresh to active/auto- refresh command period t rfc 127.5 ? 127.5 ? ns 19) table 42 timing parameter by sp eed grade - ddr2-400 & ddr2-533 parameter symbol ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 unit note 1)2)3)4)5)6) min. max. min. max.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 84 rev. 1.02, 2004-11 09112003-7yzf-nh5g precharge-all (8 banks) command period t rp t rp +1 t ck ? t rp +1 t ck ?ns 20) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 15) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 15) active bank a to active bank b command period t rrd 7.5 ? 7.5 ? ns 11)21) 10 ? 10 ? ns 13)21) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.25 ? 0.25 ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 22) write recovery time t wr 15 ? 15 ? ns internal write to read command delay t wtr 7.5 ? 10 ? ns 23) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 24) exit active power-down mode to read command (slow exit, lower power) t xards 6 - al ? 6 - al ? t ck 24) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) v ddq = 1.8v 0.1v; v dd = 1.8v 0.1v. see notes 3)4)5)6) 2) timing that is not specified is illegal and after such an ev ent, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs signals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe m ode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 8 of this data sheet. timings are further guaran teed for normal ocd drive strength (emrs(1) a1 = 0) under the reference load for timing measurements according to chapter 8.1 only. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs , rdqs / rdqs is defined in chapter 8.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 8 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refres h mode or precharge power-down mode. in case of clock frequency change during power-down, a specific procedure is required as describes in chapter 2.12 . 9) for timing definition, slew rate and slew rate derating see chapter 8.3 table 42 timing parameter by sp eed grade - ddr2-400 & ddr2-533 parameter symbol ?3.7 ddr2?533 4?4?4 ?5 ddr2?400 3?3?3 unit note 1)2)3)4)5)6) min. max. min. max.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram electrical characteristics data sheet 85 rev. 1.02, 2004-11 09112003-7yzf-nh5g note: for product nomenclature see chapter 10 of this data sheet 10) consists of data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) 4 & 8 (1k page size) 12) 8 bank device sequential activation restriction. no more than 4 banks may be activated in a rolling t faw window. 13) 16 (2k page size) 14) min ( t cl , t ch ) refers to the smaller of the actual clock low time and t he actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch) . 15) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz , t rpst ), or begins driving ( t lz , t rpre ). thz and t lz transitions occur in the same access time windows as valid data transitions.these parameters are verified by design and characterization, but not subject to production test. 16) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 o c and 95 o c. 17) 0 t case 85 o c 18) 85 o c < t case 95 o c 19) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 20) t rp(a) for a precharge-all command for an 8 bank device is equal to t rp + 1 x t ck , where t rp are the values for a single bank precharge. 21) the t rrd timing parameter depends on the page size of the dram organization. see chapter 1.5 22) the maximum limit for the t wpst parameter is not a device limit. the device op erates with a greater value for this parameter, but system performance (bus turn around) degrades accordingly. 23) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 24) user can choose two different active power-down modes for ad ditional power saving via mrs address bit a12. in ?standard active power-down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. table 43 odt ac electrical characteristics and operating conditions (all speed bins) symbol parameter / condition min. max. unit note t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac(min) t ac(max) + 1 ns ns 1) t aonpd odt turn-on (power-down modes) t ac(min) + 2 ns 2 t ck + t ac(max) + 1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac(min) t ac(max) + 0.6 ns ns 2) t aofpd odt turn-off (power-down modes) t ac(min) + 2 ns 2.5 t ck + t ac(max) + 1 ns ns t anpd odt to power down mode entry latency 3? t ck t axpd odt power down exit latency 8 ? t ck 1) odt turn on time min. is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . 2) odt turn off time min. is when the devi ce starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd .
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 86 rev. 1.02, 2004-11 09112003-7yzf-nh5g 8 ac timing measurement conditions 8.1 reference load for timing measurements figure 67 represents the timing reference load used in defining the relevant timing parameters of the device. it is not intended to either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlate the timing re ference load to a system environment. manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. this reference load is also used for output slew rate characterization. the output timing reference voltage level for single ended signals is the crosspoint with v tt . the output timing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. figure 67 reference load for timing measurements 8.2 slew rate measurement conditions 8.2.1 output slew rate for dq and single ended dqs signals output slew rate for falling and rising edges is measured between v tt ? 250 mv and v tt + 250 mv. for differential signals (dqs / dqs ) output slew rate is measured between dqs - dqs = ?500 mv and dqs ? dqs = + 500 mv. output slew rate is defined with the reference load according to figure 67 and verified by design and characterization, but not subject to production test. 8.2.2 input slew rate - differential signals input slew rate for differential signals (ck / ck , dqs / dqs , rdqs / rdqs ) for rising edges are measured from ck - ck = ?250 mv to ck ? ck = +500 mv and from ck ? ck = +250 mv to ck ? ck = ?500mv for falling edges. 25 ohm v tt = v ddq / 2 ck, ck dut timing reference points vddq dq dqs dqs rdqs rdqs
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 87 rev. 1.02, 2004-11 09112003-7yzf-nh5g 8.3 input and data setup and hold time 8.3.1 definition for input setup ( t is ) and hold time ( t ih ) address and control input setup time ( t is ) is referenced from the input signal crossing at the v ih(ac) level for a rising signal and v il(ac) for a falling signal applied to the device under test. address and control input hold time ( t ih ) is referenced from the input signal crossing at the v il(dc) level for a rising signal and v ih(dc) for a falling signal applied to the device under test. . figure 68 input setup and hold time 8.3.2 definition for data setup ( t ds ) and hold time ( t dh ), differential data strobes data input setup time ( t ds ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs/dqs signals must be monotonic between v il(dc)max and v ih(dc)min . data input hold time ( t dh ) with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the v il(dc) level to the differential data strobe crosspoint for a rising signal and v ih(dc) to the differential data strobe crosspoint for a falling sign al applied to the device under test. dqs/dqs signals must be monotonic between v il(dc)max and v ih(dc)min . figure 69 data setup and hold time (differential data strobes) v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t is t ih t is t ih ck ck v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss t ds t dh t ds t dh dqs dqs
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 88 rev. 1.02, 2004-11 09112003-7yzf-nh5g 8.3.3 definition for data setup ( t ds1 ) and hold time ( t dh1 ), single-ended data strobes data input setup time ( t ds1 ) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(ac) level to the single- ended data strobe crossing v ih/l(dc) at the start of its transition for a rising signal, and from the input signal crossing at the v il(ac) level to the single-ended data strobe crossing v ih/l(dc) at the start of its transition for a falling signal applied to the device under test. data input hold time ( tdh1) with single-ended data strobe enabled mr[bit10]=1, is referenced from the input signal crossing at the v ih(dc) level to the single-ended data strobe crossing v ih/l(ac) at the end of its transition for a rising signal and from the input signal crossing at the v il(dc) level to the single-ended data strobe crossing v ih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between v il(dc)max and v ih(dc)min . figure 70 data setup and hold time (single ended data strobes) t ds t dh t ds t dh v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss v ddq v ih(ac) min v ih(dc) min v ref v il(dc) max v il(ac) max v ss dqs dq
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 89 rev. 1.02, 2004-11 09112003-7yzf-nh5g 8.3.4 slew rate definition for input and data setup and hold times setup ( t is & t ds ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v ih(ac)min . setup ( t is & t ds ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of v il(ac)max . if the actual signal is always earlier than the nominal slew rate line between shaded ? v ref(dc) to ac region?, use nominal slew rate for derating value (see figure 71 ). if the actual signal is later than the nominal slew rate line anywhere between shaded ? v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.(see figure 72 ) hold ( t ih & t dh ) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il(dc)max and the first crossing of v ref(dc) . hold ( t ih & t dh ) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nomi nal slew rate line between shaded ?dc to v ref region?, use nominal slew rate for derating value (see figure 71 ). if the actual signal is earlier than the actual signal from the dc level to v ref level is used for derating value (see figure 72 ) . figure 71 slew rate definition nominal v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs dc to vref region vref to ac region dc to vref region vref to ac region ck, ck for tis and tih dqs, dqs for tds and tdh t is t ds t ih t dh t is t ds t ih t dh setup slew rate = vref(dc) - vil(ac)max delta tfs falling signal setup slew rate = vih(ac)min - vref(dc) delta trs rising signal hold slew rate = vref(dc) - vil(dc)max delta trh rising signal hold slew rate = vih(dc)min - vref(dc) delta tfh falling signal
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 90 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 72 slew rate definition tangent v ss v il(ac) max v il(dc) max v ref v ih(dc) min v ddq v ih(ac) min delta tfs delta trh delta tfh delta trs dc to vref region dc to vref region vref to ac region vref to ac region tangent line nominal line ck, ck for tis and tih dqs, dqs for tds and tdh t is t ds t ih t dh t is t ds t ih t dh setup slew rate = tangent line [vref(dc) - vil(ac)max] delta tfs setup slew rate = tangent line [vih(ac)min - vref(dc)] delta trs hold slew rate = tangent line [vref(dc) - vil(dc)max] delta trh hold slew rate = tangent line [vih(dc)min - vref(dc)] delta tfh falling signal falling signal rising signal rising signal
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 91 rev. 1.02, 2004-11 09112003-7yzf-nh5g 8.3.5 setup ( t is ) and hold ( t ih ) time derating tables 1. for all input signals the total input setup time and input hold time required is calculated by adding the data sheet value to the derating value respectively. example: t is (total setup tine) = t is (base) + ? t is 2. for slow slew rate the total setup time might be negative (i.e. a valid in put signal will not have reached v ih(ac) / v il(ac) at the time of the rising clock) a valid input signal is still required to complete the transition and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the next tables, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterization. table 44 input setup ( t is ) and hold ( t ih ) time derating values command / address slew rate (v/ns) ck, ck differential slew rate unit note 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih 4.0 +187 +94 +217 +124 +247 +154 ps 1) 1) for all input signals t is (total) = t is (base) + ? t is and t ih (total) = t ih (base) + ? t ih 3.5 +179 +89 +209 +119 +239 +149 ps 1) 3.0 +167 +83 +197 +113 +227 +143 ps 1) 2.5 +150 +75 +180 +105 +210 +135 ps 1) 2.0 +125 +45 +155 +75 +185 +105 ps 1) 1.5 +83 +21 +113 +51 +143 +81 ps 1) 1.0 0 0 +30 +30 +60 +60 ps 1) 0.9 ?11 ?14 +19 +16 +49 +46 ps 1) 0.8 ?25 ?31 +5 ?1 +35 +29 ps 1) 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 1) 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 1) 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 1) 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 1) 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 1) 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 1) 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 1) 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 1) 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps 1)
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ac timing measurement conditions data sheet 92 rev. 1.02, 2004-11 09112003-7yzf-nh5g table 45 data setup ( t ds ) and hold time ( t dh ) derating values for differential dqs/dqs 1)2) 1) all units in ps. 2) for all input signals t ds (total) = t ds (base) + ? t ds and t dh (total) = t dh (base) + ? t dh dq slew rate (v/ns) dqs, dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 0.8 v/ns ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh ? t ds ? t dh 2.0 +125+45+125+45+125+45??????? ????? 1.5 +83+21+83+21+83+21+95+33????? ????? 1.00 00 00 0+12+12+24+24???????? 0.9???11?14?11?14+1?2+13+10+25+22?????? 0.8 ? ? ? ? ?25 ?31 ?13 ?19 ?1 ?7 +11 +5 +23 +17 ? ? ? ? 0.7 ? ? ? ? ? ? ?31 ?42 ?19 ?30 ?7 ?18 +5 ?6 +17 +6 ? ? 0.6 ? ? ? ? ? ? ? ? ?43 ?49 ?31 ?47 ?19 ?35 ?7 ?23 +5 ?11 0.5 ? ? ? ? ? ? ? ? ? ? ?74 ?89 ?62 ?77 ?50 ?65 ?38 ?53 0.4 ? ?? ?? ????????127?140?115?128?103?116 table 46 data setup ( t ds ) and hold time ( t dh ) derating values for single ended dqs 1)2)3) 1) all units in ps. 2) for all input signals t ds1 (total) = t ds1 (base) + ? t ds1 and t dh1 (total) = t dh1 (base) + ? t dh1 3) for slow slew rate the total setup time might be negative (i.e. a valid input signal will not have reached v ih(ac) / v il(ac) at the time of the rising dqs) a valid input signal is still required to complete the transition and reach v ih(ac) / v il(ac) . for slew rates in between the values listed in the table, the derating values may be obtained by linear interpolation. these values are not subject to production test. they are verified only by design and characterization. dq slew rate (v/ns) dqs single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns ? t d1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 ? t ds1 ? t dh1 2.0+125+45+125+45+125+45------------ 1.5+83+21+83+21+83+21+95+33---------- 1.00 00000+12+12+24+24-------- 0.9- --11-14-11-14+1-2+13+10+25+22------ 0.8- -- --25-31-13-19-1-7+11+5+23+17---- 0.7- -- -- --31-42-19-30-7-18+5-6+17+6- - 0.6- -- -- ----43-49-31-47-19-35-7-23+5-11 0.5- -- -- ------74-89-62-77-50-65-38-53 0.4- -- -- --------127-140-115-128-103-116
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram package dimensions data sheet 93 rev. 1.02, 2004-11 09112003-7yzf-nh5g 9 package dimensions figure 73 package pinout p-tfbga-68 (top view) 14.4 18 x 0.8 = 20 3) 2) b 10 4) 1) 2) a 1.2 max. 0.31 min. seating plane c b ?0.46 0.05 68x ?0.15 ?0.08 c m m a 5) 1) dummy pads without ball 3) package orientation mark a1 4) bad unit marking (bum) 2) middle of packages edges 5) die sort fiducial 0.8 0.2 0.8 8 x 0.8 = 6.4 0.18 max. 0.1 c 0.1 c 2.2 max.
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram package dimensions data sheet 94 rev. 1.02, 2004-11 09112003-7yzf-nh5g figure 74 package pinout p-tfbga-92 (top view) 16 20 x 0.8 = 1) a 4) 3) b 2) 0.05 ?0.46 ?0.08 m ?0.15 92x m c ab c seating plane 2) middle of packages edges 4) bad unit marking (bum) 3) package orientation mark a1 1) dummy pads without ball 2) 20 0.8 0.2 0.8 8 x 0.8 = 6.4 10 0.18 max. c 0.1 c 0.1 0.31 min. 1.2 max. 2.2 max. 5) 5) die sort fiducial
hyb18t1g[40/80/16]0af?[3.7/5] 1-gbit double-data-rate-two sdram ddr2 component nomenclature data sheet 95 rev. 1.02, 2004-11 09112003-7yzf-nh5g 10 ddr2 component nomenclature table 47 nomenclature fields and examples example for field number 1234567891011 ddr2 dram hyb 18 t 1g 16 0 a c ?5 table 48 ddr2 dram nomenclature field description values coding 1infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?3.7 ddr2-533 ?5 ddr2-400 11 n/a for components
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